Sapatnekar, Sachin S., (1967-)

Overview

Works:	2 works in 0 publications in 0 languages

Titles

Timing by: Sapatnekar, Sachin S., (1967-); SpringerLink (Online service) (Electronic resources)

Designing digital computer systems with Verilog by: Lilja, David J.; MyiLibrary.; Sapatnekar, Sachin S., (1967-) (Electronic resources)

Subjects