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Cerny, Eduard.

概要

作品:	0 作品在 2 項出版品 1 種語言

書目資訊

The power of assertions in SystemVerilog by: Cerny, Eduard.; SpringerLink (Online service) (書目-電子資源)

SVAThe Power of Assertions in SystemVerilog / by: Cerny, Eduard.; SpringerLink (Online service) (書目-電子資源)

主題

Verilog (Computer hardware description language) SystemVerilog (Computer hardware description language) Processor Architectures. Circuits and Systems. Engineering. Electrical Engineering. Integrated circuits Electronic Circuits and Devices.

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