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晶圓級構裝重新佈線之製程最佳化及可靠度驗證 = Optimum Redi...

國立高雄大學電機工程學系--先進電子構裝技術產業研發碩士專班

晶圓級構裝重新佈線之製程最佳化及可靠度驗證 = Optimum Redistribution of Wafer Level Package and Reliability Test

紀錄類型:	書目-語言資料,印刷品 : 單行本
並列題名:	Optimum Redistribution of Wafer Level Package and Reliability Test
作者:	李佳蓉,
其他團體作者:	國立高雄大學
出版地:	[高雄市]
出版者:	撰者;
出版年:	2009[民98]
面頁冊數:	10, 51面圖，表 : 30公分;
標題:	晶圓級構裝
標題:	Wafer Level Chip Scale Package
電子資源:	http://handle.ncl.edu.tw/11296/ndltd/91151260599595653333
摘要註:	隨著個人電子產品日漸普及以及無線通訊產業的蓬勃發展，可攜及多功高度整合裝置成為電子元件構裝設計及製造的重要指標。為了增加封裝體的引腳排列密度，封裝體逐漸由傳統的邊緣排列引腳演進到陣列式排列引腳，在尺寸及成本的考量之下，封裝體尺寸逐漸縮小至晶片等級，而各封裝廠更無不積極致力於無晶片載板、無金線使用之封裝技術，因此，晶圓級構裝技術便成為目前先進電子構裝技術發展的趨勢，然而，打線封裝技術因成本考量依然會被普遍使用，為增加電子封裝設計及製程上的彈性選擇，部份晶片之接點銲墊仍保持邊緣排列設計，而邊緣排列接點銲墊之接點間距會相對縮小，無法將凸塊(錫球)直接製作於晶片銲墊之上，所以必需要利用重新佈線技術將邊緣排列之晶片銲墊轉換為陣列式排列凸塊(錫球)引腳，因此，本論文的重點在研究針對晶圓級構裝之新佈線技術之最佳化參數，提升晶圓級構裝成品的良率,並使其通過封裝等級及電路板等級之可靠度驗證。 Is popular day after day along with individual electronic products as well as the wireless communication industry vigorous development, portability and multi-function integration becomes the important target of the electronic devices design and manufacturing. Semiconductor industry have been confront with the cell design is day by day complex and small. Without doubt, the fast evolution of assembly technologies are the crucial to push forward the semiconductor industry advances to the new generation besides the development of highly integration microcircuit technology.In order to increase I/O density of IC packages, the I/O arrangement gradually from the traditional edge mode to the array mode of IC packages. In the size and under the cost actuation, package size to reduce gradually to the chip scale. Each assembly factory devotes to leave out the substrate and without gold wire use for the IC assembly technology also. The wafer level chip scale package (WLCSP) technology then therefore to form.However, when wire-bond technology is still in vogue, parts of chip design are still maintaining the peripheral mode arrangement of I/O pads on chip for the two kinds assembly technologies selection. Nevertheless, the narrow spacing of I/O pad is unable to print solder bump and drop solder ball on pads of chip directly for the peripheral mode arrangement. Therefore, implement redistribution (RDL) technology is necessary to transform the peripheral mode to into the array mode arrangement for the pad spacing enlargement.As compare with the common electronic component, the high performance analog electronic devices relatively is all severe regarding the electrical performance as well as the reliability demand. Therefore, the proposal of this article is to seeks the optimum parameters of the key assembly processes for the wafer level chip scale package of high performance electronic devices and which will enable the qualified package level and board level reliability.

晶圓級構裝重新佈線之製程最佳化及可靠度驗證 = Optimum Redistribution of Wafer Level Package and Reliability Test
李, 佳蓉

晶圓級構裝重新佈線之製程最佳化及可靠度驗證 = Optimum Redistribution of Wafer Level Package and Reliability Test / 李佳蓉撰 - [高雄市] : 撰者, 2009[民98]. - 10, 51面 ; 圖，表 ; 30公分.
參考書目：面50-51.
晶圓級構裝Wafer Level Chip Scale Package

晶圓級構裝重新佈線之製程最佳化及可靠度驗證 = Optimum Redistribution of Wafer Level Package and Reliability Test
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