國立高雄大學圖資館 |

語系: 繁體中文

說明(常見問題)

圖資館首頁

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

銲線製程能力改善與分析 = Wire Bonding process c...

國立高雄大學電機工程學系--先進電子構裝技術產業研發碩士專班

銲線製程能力改善與分析 = Wire Bonding process capability improvement and analysis

紀錄類型:	書目-語言資料,印刷品 : 單行本
並列題名:	Wire Bonding process capability improvement and analysis
作者:	朱育仁,
其他團體作者:	國立高雄大學
出版地:	[高雄市]
出版者:	撰者;
出版年:	2009[民98]
面頁冊數:	10, 53面圖，表 : 30公分;
標題:	銲線
標題:	Wire Bond
電子資源:	http://handle.ncl.edu.tw/11296/ndltd/20839831328828081243
摘要註:	在半導體業中成本競爭力是最主要的研發驅動力。單顆的晶片製程成本是直接與它的尺寸成比例的。先進的製程科技縮了小晶片尺寸致使線路活動區縮減，因此銲墊旁的可用區域相對的縮小，而又因在鋁墊下方的區域未完全運用，那是因為在銲線會有之電性傳導失敗之可靠度考量的問題。最近許多研究企圖想改善並使用鋁墊下方之空間，因而修改線路之設計之規則，鋁墊下有電路(Circuit Under Pad, CUP)元件結構被發展出來，且需求大量的驗證工作來符合可靠度水準。CUP元件結構最主要的用意是增加每片晶圓當中的產能，其中有一些是為了線路的安排及測試所特殊設計致使線路跨過鋁墊下。本論文是針對CUP 元件結構以實際封裝生產所引發之銲線製程缺點，以銲線製程中所能改善之參數、銲針，及晶圓供應商所提供之晶圓差異，利用實驗計畫等工程手法作驗證分析，改善CUP元件結構在銲線站之缺點，提升封裝良率。 Cost competitiveness is a major driving force in the semiconductor industry. The processing cost of an individual die is directly proportional to its size. Advances in processing technology have shrunk the device sizes in wire-bonded chips resulting in a smaller die core size. However the space below wire-bond pads remains relatively underutilized because of the reliability concern that electrical load transmitted during bonding can cause failures in the underlying devices. Recently studies have attempted to improve the use of space below wire-bond pads. Hence the circuits under pads (CUP) structure modified layout rules to include circuits structure under pads was developed and extensive qualification work is required to meet reliability standards. The main purpose of this paper is to investigate the damage caused by the wire bonding process of CUP devices on the in-line assembly packaging manufacture. The root cause of wire bonding failures analyzed was based on the CUP structure and several wire bond parameters; such as bonding force ultrasonic current bonding time period capillary type machine and wafer source that were also confirmed with the experiment plan of engineering technique. Finally results were also used to implement the corrective action and the assembly yield of CUP Device has been improved successfully.

銲線製程能力改善與分析 = Wire Bonding process capability improvement and analysis
朱, 育仁

銲線製程能力改善與分析 = Wire Bonding process capability improvement and analysis / 朱育仁撰 - [高雄市] : 撰者, 2009[民98]. - 10, 53面 ; 圖，表 ; 30公分.
參考書目：面53.
銲線Wire Bond

銲線製程能力改善與分析 = Wire Bonding process capability improvement and analysis
LDR:03430nam0a2200265 450 001 137194
005 20170214100804.0
009 137194
010 0 $b 精裝
100 $a 20170214y2009 k y0chiy09 e
101 1 $a chi $d chi $d eng
102 $a tw
105 $a ak m 000yy
200 1 $a 銲線製程能力改善與分析 $d Wire Bonding process capability improvement and analysis $z eng $f 朱育仁撰
210 $a [高雄市] $c 撰者 $d 2009[民98]
215 0 $a 10, 53面 $c 圖，表 $d 30公分
314 $a 指導教授：藍文厚
320 $a 參考書目：面53
328 $a 碩士論文--國立高雄大學電機工程學系--先進電子構裝技術產業研發碩士專班
330 $a 在半導體業中成本競爭力是最主要的研發驅動力。單顆的晶片製程成本是直接與它的尺寸成比例的。先進的製程科技縮了小晶片尺寸致使線路活動區縮減，因此銲墊旁的可用區域相對的縮小，而又因在鋁墊下方的區域未完全運用，那是因為在銲線會有之電性傳導失敗之可靠度考量的問題。最近許多研究企圖想改善並使用鋁墊下方之空間，因而修改線路之設計之規則，鋁墊下有電路(Circuit Under Pad, CUP)元件結構被發展出來，且需求大量的驗證工作來符合可靠度水準。CUP元件結構最主要的用意是增加每片晶圓當中的產能，其中有一些是為了線路的安排及測試所特殊設計致使線路跨過鋁墊下。本論文是針對CUP 元件結構以實際封裝生產所引發之銲線製程缺點，以銲線製程中所能改善之參數、銲針，及晶圓供應商所提供之晶圓差異，利用實驗計畫等工程手法作驗證分析，改善CUP元件結構在銲線站之缺點，提升封裝良率。 Cost competitiveness is a major driving force in the semiconductor industry. The processing cost of an individual die is directly proportional to its size. Advances in processing technology have shrunk the device sizes in wire-bonded chips resulting in a smaller die core size. However the space below wire-bond pads remains relatively underutilized because of the reliability concern that electrical load transmitted during bonding can cause failures in the underlying devices. Recently studies have attempted to improve the use of space below wire-bond pads. Hence the circuits under pads (CUP) structure modified layout rules to include circuits structure under pads was developed and extensive qualification work is required to meet reliability standards. The main purpose of this paper is to investigate the damage caused by the wire bonding process of CUP devices on the in-line assembly packaging manufacture. The root cause of wire bonding failures analyzed was based on the CUP structure and several wire bond parameters; such as bonding force ultrasonic current bonding time period capillary type machine and wafer source that were also confirmed with the experiment plan of engineering technique. Finally results were also used to implement the corrective action and the assembly yield of CUP Device has been improved successfully.
510 1 $a Wire Bonding process capability improvement and analysis $z eng
610 0 $a 銲線 $a 晶圓 $a CUP
610 1 $a Wire Bond $a Wafer $a CUP
681 $a 008M/0019 $b 542201 2502 $v 2007年版
700 1 $a 朱 $b 育仁 $4 撰 $3 170857
712 0 2 $a 國立高雄大學 $b 電機工程學系--先進電子構裝技術產業研發碩士專班 $3 170852
801 0 $a tw $b 國立高雄大學 $c 20090413 $g CCR
856 7 $z 電子資源 $2 http $u http://handle.ncl.edu.tw/11296/ndltd/20839831328828081243