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Static crosstalk noise analysis for deep sub-micron digital designs

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Static crosstalk noise analysis for deep sub-micron digital designs
作者:	Chen, Pinhong.
面頁冊數:	121 p.
附註:	Chair: Kurt Keutzer.
附註:	Source: Dissertation Abstracts International, Volume: 65-02, Section: B, page: 0915.
Contained By:	Dissertation Abstracts International65-02B.
標題:	Engineering, Electronics and Electrical.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3121429
ISBN:	0496687808

Static crosstalk noise analysis for deep sub-micron digital designs
Chen, Pinhong.

Static crosstalk noise analysis for deep sub-micron digital designs [electronic resource] - 121 p.

Chair: Kurt Keutzer.

Thesis (Ph.D.)--University of California, Berkeley, 2003.

As the feature size decreases in deep sub-micron circuit designs, coupling capacitance dominates the total capacitance, and crosstalk noise problems become significant and responsible for major timing variations and signal integrity issues.

ISBN: 0496687808Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Static crosstalk noise analysis for deep sub-micron digital designs
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520 # $a As the feature size decreases in deep sub-micron circuit designs, coupling capacitance dominates the total capacitance, and crosstalk noise problems become significant and responsible for major timing variations and signal integrity issues.
520 # $a Crosstalk coupling is also very sensitive to switching windows, in which signal nets can make transitions. It is the switching that causes the wire to inject extra current to its neighboring wires and affect their signal delay or arrival times. Thus, it is important to capture the switching windows for evaluating the crosstalk effect. However, the switching windows again depends on the signal arrival times. The way to resolve this mutual dependency is through iterations. We will build the theoretical foundation to analyze the nature of these iterations considering modeling, accuracy, and mathematical properties and also propose effective ways to converge these iterations. A time slot approach is used to reduce pessimism of crosstalk analysis.
520 # $a Crosstalk is also subject to functional correlation which is similar to the false path problem (i.e., the neighboring wires might not switch all at the same time in the same direction due to logic correlation). To evaluate a maximum crosstalk noise, we must search and compute the logic condition that produces the maximum peak noise. A conservative approach assumes every net can switch at the same time in the same direction, while the approach we propose can eliminate this false switching combination. A similar idea arises in timing analysis to eliminate false paths. However, the maximum crosstalk problem is even more complicated due to its optimization nature.
520 # $a Timing analysis is an important method to verify that a chip can meet performance requirements. Given a circuit network and its component models, timing analysis calculates signal propagation delay to verify whether the results can be delivered on time at the outputs. Unlike dynamic timing analysis, static timing analysis uses a vectorless approach to analyze the network topology without simulation. Traditional static timing analysis ignores cross coupling effects between wires, or approximates the coupling capacitance by a 2X (Miller factor) grounded decoupled capacitance to account for the worst case delay. This approach not only reduces delay calculation accuracy, but can also be shown to underestimate the delay in certain scenarios. We propose an efficient method to estimate this Miller factor so that the delay response of a decoupled circuit model can emulate the original coupling circuit. Under the assumptions of zero initial voltage, equal charge transfer, and 0.5VDD as the switching threshold voltage, an upper bound of 3X for maximum delay and a lower bound of -1X for minimum delay is proven.
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