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Electrothermal analysis of VLSI interconnects

Record Type:	Electronic resources : Monograph/item
Title/Author:	Electrothermal analysis of VLSI interconnects
Author:	Chiang, Ting-Yen.
Description:	121 p.
Notes:	Adviser: Krishan C. Saraswat.
Notes:	Source: Dissertation Abstracts International, Volume: 65-04, Section: B, page: 2007.
Contained By:	Dissertation Abstracts International65-04B.
Subject:	Engineering, Electronics and Electrical.
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3128364
ISBN:	0496756265

Electrothermal analysis of VLSI interconnects
Chiang, Ting-Yen.

Electrothermal analysis of VLSI interconnects [electronic resource] - 121 p.

Adviser: Krishan C. Saraswat.

Thesis (Ph.D.)--Stanford University, 2004.

The impact of Joule heating on the scaling trends of advanced VLSI interconnects has been evaluated in detail. Coupled analysis of reliability and delay, under the influence of thermal effects, is performed to optimize interconnect structures such as wire aspect ratio and ILD thickness. Finally, potential bottlenecks and opportunities of future heterogeneous three dimensional (3-D) ICs with various integration scenarios are identified from the thermal point of view. It is shown that under certain scenarios, 3-D ICs can actually lead to better thermal performance than planar (2-D) ICs. Tradeoffs among power, performance, chip real estate and thermal impact for 3-D ICs are evaluated.

ISBN: 0496756265Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Electrothermal analysis of VLSI interconnects
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502 $a Thesis (Ph.D.)--Stanford University, 2004.
520 # $a The impact of Joule heating on the scaling trends of advanced VLSI interconnects has been evaluated in detail. Coupled analysis of reliability and delay, under the influence of thermal effects, is performed to optimize interconnect structures such as wire aspect ratio and ILD thickness. Finally, potential bottlenecks and opportunities of future heterogeneous three dimensional (3-D) ICs with various integration scenarios are identified from the thermal point of view. It is shown that under certain scenarios, 3-D ICs can actually lead to better thermal performance than planar (2-D) ICs. Tradeoffs among power, performance, chip real estate and thermal impact for 3-D ICs are evaluated.
520 # $a The scaling of VLSI structures leads to continuous increase in current density that results in ever greater interconnect Joule heating. In addition, a variety of low-k materials have been introduced to reduce the RC delay, dynamic power consumption and crosstalk noise in advanced technology. Together with the poor thermal conductivity of such materials and more metal levels added, the increasing thermal impedance further exacerbates temperature rise in interconnects. As a result, not only will thermal effects be a major reliability concern, but also the increase of resistivity with temperature can degrade the expected speed performance. On the other hand, overly pessimistic estimation of the interconnect temperature will lead to overly conservative approach. Hence, performing a more realistic thermal modeling and analysis of interconnects is critical.
520 # $a This research proposes both compact analytical models and fast SPICE based 3-D electro-thermal simulation methodology to characterize thermal effects due to Joule heating in high performance Cu/low k interconnects under steady-state and transient stress conditions. The results demonstrate excellent agreement with experimental data and those using Finite Element (FE) thermal simulations (ANSYS). The effect of vias, as efficient heat transfer paths to alleviate the temperature rise in the metal wires, is included in our analysis for the first time to provide more accurate and realistic thermal diagnosis. It shows that the effectiveness of vias in reducing the temperature rise in interconnects is highly dependent on the via separation and the dielectric materials used.
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