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System-on-chip test architecturesnan...

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System-on-chip test architecturesnanometer design for testability /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	System-on-chip test architecturesedited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba.
其他題名:	nanometer design for testability /
其他作者:	Touba, Nur A.
出版者:	Amsterdam ;Morgan Kaufmann Publishers,c2008.
面頁冊數:	xxxvi, 856 p. :ill. ;25 cm.
叢書名:	The Morgan Kaufmann series in systems on silicon
標題:	Systems on a chipTesting.
電子資源:	An electronic book accessible through the World Wide Web; click for information
電子資源:	http://www.engineeringvillage.com/controller/servlet/OpenURL?genre=book&isbn=9780123739735
電子資源:	http://www.loc.gov/catdir/toc/ecip0719/2007023373.html
電子資源:	http://www.loc.gov/catdir/enhancements/fy0808/2007023373-d.html
ISBN:	9780123739735

System-on-chip test architecturesnanometer design for testability /
System-on-chip test architecturesnanometer design for testability /[electronic resource] :edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba. - Amsterdam ;Morgan Kaufmann Publishers,c2008. - xxxvi, 856 p. :ill. ;25 cm. - The Morgan Kaufmann series in systems on silicon.

Includes bibliographical references and index.

Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students.

Electronic reproduction.
Amsterdam :
Elsevier Science & Technology,
2008.

Mode of access: World Wide Web.

ISBN: 9780123739735

Source: 137803:137940Elsevier Science & Technologyhttp://www.sciencedirect.comSubjects--Topical Terms:

282410
Systems on a chip
--Testing.Index Terms--Genre/Form:

214472
Electronic books.

LC Class. No.: TK7895.E42 / S978 2008eb

Dewey Class. No.: 621.39/5

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245 0 0 $a System-on-chip test architectures $h [electronic resource] : $b nanometer design for testability / $c edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba.
260 $a Amsterdam ; $a Boston : $c c2008. $b Morgan Kaufmann Publishers,
300 $a xxxvi, 856 p. : $b ill. ; $c 25 cm.
440 4 $a The Morgan Kaufmann series in systems on silicon
504 $a Includes bibliographical references and index.
505 0 $a Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends.
520 $a Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students.
533 $a Electronic reproduction. $b Amsterdam : $c Elsevier Science & Technology, $d 2008. $n Mode of access: World Wide Web. $n System requirements: Web browser. $n Title from title screen (viewed on May 14, 2008). $n Access may be restricted to users at subscribing institutions.
650 0 $a Systems on a chip $x Testing. $3 282410
650 0 $a Integrated circuits $x Very large scale integration $x Testing. $3 182401
650 0 $a Integrated circuits $x Very large scale integration $x Design. $3 257763
655 7 $a Electronic books. $2 local. $3 214472
700 1 $a Touba, Nur A. $3 341104
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856 4 0 $3 ScienceDirect $u http://www.sciencedirect.com/science/book/9780123739735 $z An electronic book accessible through the World Wide Web; click for information
856 4 0 $3 Referex $u http://www.engineeringvillage.com/controller/servlet/OpenURL?genre=book&isbn=9780123739735 $z An electronic book accessible through the World Wide Web; click for information
856 4 1 $3 Table of contents only $u http://www.loc.gov/catdir/toc/ecip0719/2007023373.html
856 4 2 $3 Publisher description $u http://www.loc.gov/catdir/enhancements/fy0808/2007023373-d.html
994 $a C0 $b TEF

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http://www.sciencedirect.com/science/book/9780123739735
http://www.engineeringvillage.com/controller/servlet/OpenURL?genre=book&isbn=9780123739735
http://www.loc.gov/catdir/toc/ecip0719/2007023373.html
http://www.loc.gov/catdir/enhancements/fy0808/2007023373-d.html

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