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Logic synthesis and verification alg...

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Hachtel, Gary D.

Logic synthesis and verification algorithms

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Logic synthesis and verification algorithmsby Gary D. Hachtel, Fabio Somenzi.
作者:	Hachtel, Gary D.
其他作者:	Somenzi, Fabio.
出版者:	Boston :Kluwer Academic Publishers,c2002.
面頁冊數:	xxxi, 564 p. :ill., digital ;26 cm.
Contained By:	Springer e-books
標題:	Logic designData processing.
電子資源:	http://dx.doi.org/10.1007/b117060
ISBN:	9780306475924 (electronic bk.)

Logic synthesis and verification algorithms
Hachtel, Gary D.

Logic synthesis and verification algorithms[electronic resource] /by Gary D. Hachtel, Fabio Somenzi. - Boston :Kluwer Academic Publishers,c2002. - xxxi, 564 p. :ill., digital ;26 cm.

ISBN: 9780306475924 (electronic bk.)Subjects--Topical Terms:

182348
Logic design
--Data processing.

LC Class. No.: TK7874.75 / .H33 2002

Dewey Class. No.: 621.395

Logic synthesis and verification algorithms
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100 1 $a Hachtel, Gary D. $3 185513
245 1 0 $a Logic synthesis and verification algorithms $h [electronic resource] / $c by Gary D. Hachtel, Fabio Somenzi.
260 $a Boston : $b Kluwer Academic Publishers, $c c2002.
300 $a xxxi, 564 p. : $b ill., digital ; $c 26 cm.
650 0 $a Logic design $x Data processing. $3 182348
650 0 $a Computer-aided design. $3 181931
650 0 $a Integrated circuits $x Verification. $3 185514
650 0 $a Integrated circuits $x Very large scale integration $x Design $x Data processing. $3 184718
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856 4 0 $u http://dx.doi.org/10.1007/b117060
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http://dx.doi.org/10.1007/b117060

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