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Value prediction in many-core systems.

Liu, Shaoshan.

Value prediction in many-core systems.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Value prediction in many-core systems.
作者:	Liu, Shaoshan.
面頁冊數:	132 p.
附註:	Source: Dissertation Abstracts International, Volume: 71-03, Section: B, page: 1902.
附註:	Adviser: Jean-Luc Gaudiot.
Contained By:	Dissertation Abstracts International71-03B.
標題:	Engineering, Computer.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3396579
ISBN:	9781109648768

Value prediction in many-core systems.
Liu, Shaoshan.

Value prediction in many-core systems. - 132 p.

Source: Dissertation Abstracts International, Volume: 71-03, Section: B, page: 1902.

Thesis (Ph.D.)--University of California, Irvine, 2010.

Modern many-core-on-a-chip designs will demand programs with extremely high degrees of parallelism. Our study of the PARSEC and the SPLASH-2 benchmark suites has shown that application programs may not have sufficient inherent parallelism. However, two fundamental factors contribute to program speedup: intrinsic parallelism, which can be exploited by fine-grained synchronization, and inherent data redundancy, which can be exploited by value prediction. In this work, we first present a theoretical framework to characterize the predictability of data values and the feasibilities of value predictor designs. The results are encouraging: our theoretical analysis shows that the average value prediction accuracy can reach 70% on the PARSEC and the SPLASH-2 benchmarks. This demonstrates the immense potential of value prediction in enhancing the performance of many-core architectures.

ISBN: 9781109648768Subjects--Topical Terms:

384375
Engineering, Computer.

Value prediction in many-core systems.
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500 $a Source: Dissertation Abstracts International, Volume: 71-03, Section: B, page: 1902.
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520 $a Modern many-core-on-a-chip designs will demand programs with extremely high degrees of parallelism. Our study of the PARSEC and the SPLASH-2 benchmark suites has shown that application programs may not have sufficient inherent parallelism. However, two fundamental factors contribute to program speedup: intrinsic parallelism, which can be exploited by fine-grained synchronization, and inherent data redundancy, which can be exploited by value prediction. In this work, we first present a theoretical framework to characterize the predictability of data values and the feasibilities of value predictor designs. The results are encouraging: our theoretical analysis shows that the average value prediction accuracy can reach 70% on the PARSEC and the SPLASH-2 benchmarks. This demonstrates the immense potential of value prediction in enhancing the performance of many-core architectures.
520 $a Also, we explore the possibility of using the many-core GPU architectures for speculative execution: we implement software value prediction techniques to accelerate programs with limited parallelism, and software speculation techniques to accelerate programs that contain runtime parallelism, which are hard to parallelize statically. Our experiment results show that due to the relatively high overhead, mapping software value prediction techniques on existing GPUs may not bring any immediate performance gain. On the other hand, although software speculation techniques introduce some overhead as well, mapping these techniques to existing GPUs can already bring some performance gain over CPU. Furthermore, we explore the hardware implementation of speculative execution operations on GPU architectures. The results indicate that the hardware extensions result in almost 10-fold reduction of the control divergent sequential operations with only moderate hardware and power consumption overheads.
520 $a In addition, communication problems have become a major performance bottleneck in many-core architectures and in large-scale scientific simulations. We use LQCD simulations as a case study to study how value prediction techniques can reduce the communication overheads. We first implement a software value predictor on LQCD simulations: 22.15% of the predictions result in performance gain and only 2.65% of the predictions lead to rollbacks. Then we explore the hardware value predictor design, which results in a 6-fold reduction of the prediction latency. Moreover, based on the observation that the full range of floating point accuracy may not be always needed, we propose and implement an initial design of the tolerance value predictor: as the tolerance range increases, the prediction accuracy also increases dramatically.
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