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High-level verificationmethods and t...

Gupta, Rajesh K.

High-level verificationmethods and tools for verification of system-level designs /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	High-level verificationby Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta.
其他題名:	methods and tools for verification of system-level designs /
作者:	Kundu, Sudipta.
其他作者:	Lerner, Sorin.
出版者:	New York, NY :Springer Science+Business Media, LLC,2011.
面頁冊數:	xiii, 167 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
標題:	Integrated circuitsVerification.
電子資源:	http://dx.doi.org/10.1007/978-1-4419-9359-5
ISBN:	9781441993595 (electronic bk.)

High-level verificationmethods and tools for verification of system-level designs /
Kundu, Sudipta.

High-level verificationmethods and tools for verification of system-level designs /[electronic resource] :by Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta. - New York, NY :Springer Science+Business Media, LLC,2011. - xiii, 167 p. :ill., digital ;24 cm.

ISBN: 9781441993595 (electronic bk.)Subjects--Topical Terms:

185514
Integrated circuits
--Verification.

LC Class. No.: TK7874.58 / .K86 2011

Dewey Class. No.: 621.382

High-level verificationmethods and tools for verification of system-level designs /
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