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High-level verificationmethods and t...
~
Gupta, Rajesh K.
High-level verificationmethods and tools for verification of system-level designs /
Record Type:
Electronic resources : Monograph/item
Title/Author:
High-level verificationby Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta.
Reminder of title:
methods and tools for verification of system-level designs /
Author:
Kundu, Sudipta.
other author:
Lerner, Sorin.
Published:
New York, NY :Springer Science+Business Media, LLC,2011.
Description:
xiii, 167 p. :ill., digital ;24 cm.
Contained By:
Springer eBooks
Subject:
Integrated circuitsVerification.
Online resource:
http://dx.doi.org/10.1007/978-1-4419-9359-5
ISBN:
9781441993595 (electronic bk.)
High-level verificationmethods and tools for verification of system-level designs /
Kundu, Sudipta.
High-level verification
methods and tools for verification of system-level designs /[electronic resource] :by Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta. - New York, NY :Springer Science+Business Media, LLC,2011. - xiii, 167 p. :ill., digital ;24 cm.
ISBN: 9781441993595 (electronic bk.)Subjects--Topical Terms:
185514
Integrated circuits
--Verification.
LC Class. No.: TK7874.58 / .K86 2011
Dewey Class. No.: 621.382
High-level verificationmethods and tools for verification of system-level designs /
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methods and tools for verification of system-level designs /
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by Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta.
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Integrated circuits
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Engineering (Springer-11647)
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000000056206
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EB TK7874.58 .K86 2011
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1 records • Pages 1 •
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http://dx.doi.org/10.1007/978-1-4419-9359-5
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