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Advanced Model Order Reduction Techn...
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Ebooks Corporation.
Advanced Model Order Reduction Techniques in VLSI Design.
紀錄類型:
書目-電子資源 : Monograph/item
正題名/作者:
Advanced Model Order Reduction Techniques in VLSI Design.
作者:
Tan, Sheldon.
其他作者:
He, Lei.
出版者:
Leiden :Cambridge University Press,2007.
面頁冊數:
260 p.
電子資源:
Click here to view book
ISBN:
9780511541117 (electronic bk.)
Advanced Model Order Reduction Techniques in VLSI Design.
Tan, Sheldon.
Advanced Model Order Reduction Techniques in VLSI Design.
[electronic resource]. - Leiden :Cambridge University Press,2007. - 260 p.
Cover; Half-title; Title; Copyright; Contents; Figures; Tables; Foreword; Acknowledgments; 1 Introduction; 2 Projection-based model order reduction algorithms; 3 Truncated balanced realization methods for MOR; 4 Passive balanced truncation of linear systems in descriptor form; 5 Passive hierarchical model order reduction; 6 Terminal reduction of linear dynamic circuits; 7 Vector-potential equivalent circuit for inductance modeling; 8 Structure-preserving model order reduction; 9 Block structure-preserving reduction for RLCK circuits; 10 Model optimization and passivity enforcement
Systematic introduction to key model order reduction techniques in linear circuits, using real-world examples to illustrate advantages and disadvantages.?
Electronic reproduction.
Available via World Wide Web.
Mode of access: World Wide Web.
ISBN: 9780511541117 (electronic bk.)Index Terms--Genre/Form:
214472
Electronic books.
LC Class. No.: TK7874.75 . / T36 2007
Dewey Class. No.: 621.395
Advanced Model Order Reduction Techniques in VLSI Design.
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Cover; Half-title; Title; Copyright; Contents; Figures; Tables; Foreword; Acknowledgments; 1 Introduction; 2 Projection-based model order reduction algorithms; 3 Truncated balanced realization methods for MOR; 4 Passive balanced truncation of linear systems in descriptor form; 5 Passive hierarchical model order reduction; 6 Terminal reduction of linear dynamic circuits; 7 Vector-potential equivalent circuit for inductance modeling; 8 Structure-preserving model order reduction; 9 Block structure-preserving reduction for RLCK circuits; 10 Model optimization and passivity enforcement
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11 General multi-port circuit realization12 Reduction for multi-terminal interconnect circuits; 13 Passive modeling by signal waveform shaping; References; Index
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http://dx.doi.org/10.1017/CBO9780511541117
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