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Noise Figure Optimization of Fully I...
~
Ibrahim, Mohamed Farhat.
Noise Figure Optimization of Fully Integrated Inductively Degenerated Silicon Germanium HBT LNAs.
紀錄類型:
書目-電子資源 : Monograph/item
正題名/作者:
Noise Figure Optimization of Fully Integrated Inductively Degenerated Silicon Germanium HBT LNAs.
作者:
Ibrahim, Mohamed Farhat.
面頁冊數:
224 p.
附註:
Source: Dissertation Abstracts International, Volume: 73-10(E), Section: B.
附註:
Adviser: Jim Haslett.
Contained By:
Dissertation Abstracts International73-10B(E).
標題:
Engineering, Aerospace.
電子資源:
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=NR83530
ISBN:
9780494835302
Noise Figure Optimization of Fully Integrated Inductively Degenerated Silicon Germanium HBT LNAs.
Ibrahim, Mohamed Farhat.
Noise Figure Optimization of Fully Integrated Inductively Degenerated Silicon Germanium HBT LNAs.
- 224 p.
Source: Dissertation Abstracts International, Volume: 73-10(E), Section: B.
Thesis (Ph.D.)--University of Calgary (Canada), 2012.
Silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) have the properties of producing very low noise and high gain over a wide bandwidth. Because of these properties, SiGe HBTs have continually improved and now compete with InP and GaAs HEMTs for low-noise amplification.
ISBN: 9780494835302Subjects--Topical Terms:
227946
Engineering, Aerospace.
Noise Figure Optimization of Fully Integrated Inductively Degenerated Silicon Germanium HBT LNAs.
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Silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) have the properties of producing very low noise and high gain over a wide bandwidth. Because of these properties, SiGe HBTs have continually improved and now compete with InP and GaAs HEMTs for low-noise amplification.
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This thesis investigates the theoretical characterizations and optimizations of SiGe HBT low noise amplifiers (LNAs) for low-noise low-power applications, using SiGe BiCMOS (bipolar complementary metal-oxide-semiconductor) technology.
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The theoretical characterization of SiGe HBT transistors is investigated by a comprehensive study of the DC and small-signal transistor modeling.
520
$a
Based on a selected small-signal model, a noise model for the SiGe HBT transistor is produced. This noise model is used to build a cascode inductively degenerated SiGe HBT LNA circuit. The noise figure (NF) equation for this LNA is derived. This NF equation shows better than 94.4% agreement with the simulation results.
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With the small-signal model verification, a new analytical method for optimizing the noise figure of the SiGe HBT LNA circuits is presented. The novelty feature of this optimization is the inclusion of the noise contributions of the base inductor parasitic resistance, the emitter inductor parasitic resistance and the bond-wire inductor parasitic resistances.
520
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The optimization is performed by reducing the number of design variables as possible. This improved theoretical optimization results in LNA designs that achieve better noise figure performance compared to previously published results in bipolar and BiCMOS technologies.
520
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Different design constraints are discussed for the LNA optimization techniques. Three different LNAs are designed. The three designs are fully integrated and fabricated in a single chip to achieve a fully monolithic realization.
520
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The LNA designs are experimentally verified. The low noise design produced a NF of 1.5dB, S21 of 15dB, and power consumption of 15mW. The three LNA designs occupied 1.4mum 2 in 130 nm BiCMOS technology.
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