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濺鍍製程矽穿導孔之階梯覆蓋率研究 = Step Coverage Stu...

國立高雄大學電機工程學系--先進電子構裝技術產業研發碩士專班

濺鍍製程矽穿導孔之階梯覆蓋率研究 = Step Coverage Study of Through Silicon Via in Sputter Process

紀錄類型:	書目-語言資料,印刷品 : 單行本
並列題名:	Step Coverage Study of Through Silicon Via in Sputter Process
作者:	廖崇亨,
其他團體作者:	國立高雄大學
出版地:	[高雄市]
出版者:	撰者;
出版年:	2015[民104]
面頁冊數:	69面圖，表 : 30公分;
標題:	濺鍍沉積
標題:	step coverage
電子資源:	http://handle.ncl.edu.tw/11296/ndltd/39142643601515938694
附註:	104年10月31日公開
附註:	參考書目：面60
摘要註:	本論文是以不同開孔寬度及深度矽穿導孔對於濺鍍階梯覆蓋率之影響作為主題進行研討。首先,分別調校不同載盤功率及沉積壓力之製程參數,探討其對於濺鍍金屬薄膜的不均勻度之影響,並找出最低不均勻度之單層鈦與銅金屬薄膜製程條件,且決定鈦-銅疊層金屬之濺鍍參數。之後,選擇三種不同開孔寬度及深度的矽穿導孔進行濺鍍沉積該金屬薄膜,再以研磨之方式,使用晶圓級電子顯微鏡進行觀察其切面,在濺鍍固定的鈦-銅疊層金屬薄膜厚度條件下,對於三種不同開孔寬度及深度矽穿導孔對於鈦-銅疊層金屬薄膜之階梯覆蓋率影響進行研究探討。 This thesis studied the step coverage performance of titanium-copper (Ti-Cu) in silicon wafer with different via width and depth in sputter process. The film uniformities in the deposition of Ti and Cu respectively with different platen power and chamber pressure were studied first. With this, the optimal parameters were selected for further stacked Ti-Cu deposition process. The step coverage for the Ti-Cu on the through silicon via (TSV) was studied then with three different width and depth. The TSV cross-section was characterized by scanning electron microscope (SEM) at different positions. The Ti-Cu coverage behavior on TSV were discussed and the well coverage performance be achieved with controlled parameters.

濺鍍製程矽穿導孔之階梯覆蓋率研究 = Step Coverage Study of Through Silicon Via in Sputter Process
廖, 崇亨

濺鍍製程矽穿導孔之階梯覆蓋率研究 = Step Coverage Study of Through Silicon Via in Sputter Process / 廖崇亨撰 - [高雄市] : 撰者, 2015[民104]. - 69面 ; 圖，表 ; 30公分.
104年10月31日公開參考書目：面60.
濺鍍沉積step coverage

濺鍍製程矽穿導孔之階梯覆蓋率研究 = Step Coverage Study of Through Silicon Via in Sputter Process
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