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60GHz Integrated On-chip Antenna on ...

Bereka, Desalegn B.

60GHz Integrated On-chip Antenna on Silicon for High Speed Applications.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	60GHz Integrated On-chip Antenna on Silicon for High Speed Applications.
作者:	Bereka, Desalegn B.
面頁冊數:	155 p.
附註:	Source: Dissertation Abstracts International, Volume: 77-03(E), Section: B.
附註:	Adviser: Anand Gopinath.
Contained By:	Dissertation Abstracts International77-03B(E).
標題:	Engineering.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3727864
ISBN:	9781339131191

60GHz Integrated On-chip Antenna on Silicon for High Speed Applications.
Bereka, Desalegn B.

60GHz Integrated On-chip Antenna on Silicon for High Speed Applications. - 155 p.

Source: Dissertation Abstracts International, Volume: 77-03(E), Section: B.

Thesis (Ph.D.)--University of Minnesota, 2015.

The recent release of the unlicensed 60 GHz band tackles the increasing demand for more bandwidth in the wireless consumer electronics market. In order to meet the cost requirements of this market, many research groups have worked towards 60 GHz front-end electronics in mainstream silicon technologies, i.e., CMOS and BiCMOS. However, the technology choice for suitable antennas has not been as unitary and is controversially discussed. While there is a wide consensus that the antenna should be integrated in the same package with the front-end integrated circuit (IC), there are three main approaches on the realization. First, there is the Antenna-in-Package approach, in which the antenna is implemented in the IC's packaging technology. Second, there is the Antenna-on-Chip approach, in which the antenna is directly implemented in the back-end of the IC. Finally, the third approach can be considered as a hybrid of Antenna-on-Chip and Antenna-in-Package, in which the feed-point of the antenna is implemented on-chip while the radiating element itself is realized off-chip.

ISBN: 9781339131191Subjects--Topical Terms:

210888
Engineering.

60GHz Integrated On-chip Antenna on Silicon for High Speed Applications.
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245 1 0 $a 60GHz Integrated On-chip Antenna on Silicon for High Speed Applications.
300 $a 155 p.
500 $a Source: Dissertation Abstracts International, Volume: 77-03(E), Section: B.
500 $a Adviser: Anand Gopinath.
502 $a Thesis (Ph.D.)--University of Minnesota, 2015.
520 $a The recent release of the unlicensed 60 GHz band tackles the increasing demand for more bandwidth in the wireless consumer electronics market. In order to meet the cost requirements of this market, many research groups have worked towards 60 GHz front-end electronics in mainstream silicon technologies, i.e., CMOS and BiCMOS. However, the technology choice for suitable antennas has not been as unitary and is controversially discussed. While there is a wide consensus that the antenna should be integrated in the same package with the front-end integrated circuit (IC), there are three main approaches on the realization. First, there is the Antenna-in-Package approach, in which the antenna is implemented in the IC's packaging technology. Second, there is the Antenna-on-Chip approach, in which the antenna is directly implemented in the back-end of the IC. Finally, the third approach can be considered as a hybrid of Antenna-on-Chip and Antenna-in-Package, in which the feed-point of the antenna is implemented on-chip while the radiating element itself is realized off-chip.
520 $a This thesis focuses Antenna-on chip main integration strategies. Its goal is to explore the challenges and potentials of this technology with respect to millimeter-wave antenna integration. For this, integrated antenna concepts for the 60 GHz band are developed using mainstream technologies. This restriction is necessary in order to achieve cost-effective solutions for the highly price-competitive wireless consumer electronics market. The main challenge of antenna design in a planar technology is the trade-off between radiation efficiency and bandwidth. To obtain a large bandwidth, a relatively thick dielectric layer is needed. However, a thicker dielectric layer introduces more losses due to surface-wave excitation in the dielectric. Silicon with low resistivity substrates also introduce special challenges for high efficiency millimeter wave on-chip antennas. First, their low resistivity of 0.1-20 O-cm results in high dielectric loss and significantly reduces the antenna efficiency. Second, TE and TM surface waves are easily triggered in 200-500 ?m thick silicon substrates and can have serious detrimental effects on the antenna pattern and efficiency. A lot of work has been done to improve the radiation efficiency of planar antennas while maintaining a large bandwidth. Particularly, the use of electromagnetic band gap (EBG) materials that suppress the surface-wave excitation has received a lot of attention. However, EBG materials are either difficult to manufacture, or too large to be used in planar array configurations. Another approach to improve the radiation efficiency is presented in literatures, where a superstrate antenna is used. This solution shows good performance. But careful consideration reveals that most designs are not readily amenable to mass production and many purposed structures are very inefficient. Some designs which are efficient require extra process steps such as trenching. This extra process hinders to achieve truly low fabrication cost. The fabrication process should be fully compatible with current substrate processing technology.
520 $a To tackle these challenges, antenna on chip (AOC) structures, named virtual loop antenna (VLA) structures, were studied and utilized for low profile Si CMOS on-chip antenna design and realization. The concept proposed in this work avoids the extra steps but provides for comparable good antenna efficiency. We propose the design of this antenna for use on CMOS ICs technology that promises to integrate a complete 60GHz system on single chip that combines a good performance in both bandwidth and radiation efficiency. The resulting design is completely planar, and the use of vias is avoided. This result in inherently low fabrication cost, light weight, and low volume antenna. Its design is essentially a joint optimization of bandwidth and power efficiency. The design of this integrated loop antenna for use on 60GHz CMOS receivers was based on silicon substrates of low resistivity that varies from 5-20O-cm. The design was based on intensive electromagnetic simulations using HFSS software package. The width and length of the antenna is less than half a free-space wavelength, such that the antenna can be readily used for the realization of a planar beam-forming array. The designed antenna was fabricated and the measurement results agree with those of simulation results.
590 $a School code: 0130.
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650 4 $a Electrical engineering. $3 454503
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710 2 $a University of Minnesota. $b Electrical Engineering. $3 492856
773 0 $t Dissertation Abstracts International $g 77-03B(E).
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