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Silicon nanowire transistors

Bindal, Ahmet.

Silicon nanowire transistors

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Silicon nanowire transistorsby Ahmet Bindal, Sotoudeh Hamedi-Hagh.
作者:	Bindal, Ahmet.
其他作者:	Hamedi-Hagh, Sotoudeh.
出版者:	Cham :Springer International Publishing :2016.
面頁冊數:	xiv, 165 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
標題:	Nanowires.
電子資源:	http://dx.doi.org/10.1007/978-3-319-27177-4
ISBN:	9783319271774$q(electronic bk.)

Silicon nanowire transistors
Bindal, Ahmet.

Silicon nanowire transistors[electronic resource] /by Ahmet Bindal, Sotoudeh Hamedi-Hagh. - Cham :Springer International Publishing :2016. - xiv, 165 p. :ill., digital ;24 cm.

Dual Work Function Silicon Nanowire MOS Transistors -- Single Work Function Silicon Nanowire MOS Transistors -- Spice Modeling For Analog and Digital Applications -- High-Speed Analog Applications -- Radio Frequency (RF) Applications -- SRAM Mega Cell Design for Digital Applications -- Field-Programmable-Gate-Array (FPGA) -- Integrate-And-Fire Spiking (IFS) Neuron -- Direct Sequence Spread Spectrum (DSSS) Base-Band Transmitter.

This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology's true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types of memory on the same chip, such as capacitive cells and transistors with floating gates that can be used as DRAMs and Flash memories.

ISBN: 9783319271774$q(electronic bk.)

Standard No.: 10.1007/978-3-319-27177-4doiSubjects--Topical Terms:

205034
Nanowires.

LC Class. No.: TK7874.85

Dewey Class. No.: 621.3815

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520 $a This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology's true potential for the next generation VLSI. Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types of memory on the same chip, such as capacitive cells and transistors with floating gates that can be used as DRAMs and Flash memories.
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