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Complete symbolic simulation of Syst...

Herdt, Vladimir.

Complete symbolic simulation of SystemC modelsefficient formal verification of finite non-terminating programs /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Complete symbolic simulation of SystemC modelsby Vladimir Herdt.
其他題名:	efficient formal verification of finite non-terminating programs /
作者:	Herdt, Vladimir.
出版者:	Wiesbaden :Springer Fachmedien Wiesbaden :2016.
面頁冊數:	xix, 162 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
標題:	Formal methods (Computer science)
電子資源:	http://dx.doi.org/10.1007/978-3-658-12680-3
ISBN:	9783658126803$q(electronic bk.)

Complete symbolic simulation of SystemC modelsefficient formal verification of finite non-terminating programs /
Herdt, Vladimir.

Complete symbolic simulation of SystemC modelsefficient formal verification of finite non-terminating programs /[electronic resource] :by Vladimir Herdt. - Wiesbaden :Springer Fachmedien Wiesbaden :2016. - xix, 162 p. :ill., digital ;24 cm. - BestMasters. - BestMasters..

Verification of Systems -- Introduction to Formal Verification of SystemC Models -- Symbolic Model Checking with Partial Order Reduction -- Efficient Symbolic State Matching using State Subsumption -- Heuristic Approaches for Symbolic State Matching -- Evaluation of Proposed Techniques.

In his master thesis, Vladimir Herdt presents a novel approach, called complete symbolic simulation, for a more efficient verification of much larger (non-terminating) SystemC programs. The approach combines symbolic simulation with stateful model checking and allows to verify safety properties in (cyclic) finite state spaces, by exhaustive exploration of all possible inputs and process schedulings. The state explosion problem is alleviated by integrating two complementary reduction techniques. Compared to existing approaches, the complete symbolic simulation works more efficiently, and therefore can provide correctness proofs for larger systems, which is one of the most challenging tasks, due to the ever increasing complexity. Contents Verification of Systems Introduction to Formal Verification of SystemC Models Symbolic Model Checking with Partial Order Reduction Efficient Symbolic State Matching using State Subsumption Heuristic Approaches for Symbolic State Matching Evaluation of Proposed Techniques Target Groups Lecturers and Students of Computer Sciences and Electrical Engineering Hardware Designers and Verification Engineers using SystemC The Author Vladimir Herdt is working as Research Assistant in the Group of Computer Architecture at the University of Bremen, where he is pursuing his PhD degree.

ISBN: 9783658126803$q(electronic bk.)

Standard No.: 10.1007/978-3-658-12680-3doiSubjects--Topical Terms:

277520
Formal methods (Computer science)

LC Class. No.: QA76.9.F67

Dewey Class. No.: 004.0151

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