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I/O processing for Cyber Physical Sy...

Nguyen, Hoang.

I/O processing for Cyber Physical System using scratchpad memory.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	I/O processing for Cyber Physical System using scratchpad memory.
作者:	Nguyen, Hoang.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, 2016
面頁冊數:	77 p.
附註:	Source: Masters Abstracts International, Volume: 55-05.
附註:	Adviser: Hakduran Koc.
Contained By:	Masters Abstracts International55-05(E).
標題:	Computer engineering.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10133515
ISBN:	9781339920900

I/O processing for Cyber Physical System using scratchpad memory.
Nguyen, Hoang.

I/O processing for Cyber Physical System using scratchpad memory. - Ann Arbor : ProQuest Dissertations & Theses, 2016 - 77 p.

Source: Masters Abstracts International, Volume: 55-05.

Thesis (M.S.)--University of Houston-Clear Lake, 2016.

Cyber Physical System (CPS) is an integration of an embedded system with network coupled tightly with physical processes and is considered as the next generation of embedded systems. As a CPS needs to respond simultaneously to the changes in the environment that it is monitoring, the computational cost and real-time constraints are the main challenges and important factors when designing an effective CPS. To overcome these challenges, Chip Multi-Processors (CMP) have been used to enhance the overall system performance by exploring the computational parallelism. Nevertheless, the performance of the whole system is still constrained by the overhead of data transfers between sensors/actuators and processors. While CMP just needs about a few microseconds to execute the control algorithm to make a decision, it may need tens of microseconds to copy the dataset among sensors/actuators, external memory, and internal memory of CMP [22].

ISBN: 9781339920900Subjects--Topical Terms:

212944
Computer engineering.

I/O processing for Cyber Physical System using scratchpad memory.
LDR:03021nmm a2200325 4500 001 502099
005 20170619070725.5
008 170818s2016 ||||||||||||||||| ||eng d
020 $a 9781339920900
035 $a (MiAaPQ)AAI10133515
035 $a AAI10133515
040 $a MiAaPQ $c MiAaPQ
100 1 $a Nguyen, Hoang. $3 766102
245 1 0 $a I/O processing for Cyber Physical System using scratchpad memory.
260 $a Ann Arbor : $b ProQuest Dissertations & Theses, $c 2016
300 $a 77 p.
500 $a Source: Masters Abstracts International, Volume: 55-05.
500 $a Adviser: Hakduran Koc.
502 $a Thesis (M.S.)--University of Houston-Clear Lake, 2016.
520 $a Cyber Physical System (CPS) is an integration of an embedded system with network coupled tightly with physical processes and is considered as the next generation of embedded systems. As a CPS needs to respond simultaneously to the changes in the environment that it is monitoring, the computational cost and real-time constraints are the main challenges and important factors when designing an effective CPS. To overcome these challenges, Chip Multi-Processors (CMP) have been used to enhance the overall system performance by exploring the computational parallelism. Nevertheless, the performance of the whole system is still constrained by the overhead of data transfers between sensors/actuators and processors. While CMP just needs about a few microseconds to execute the control algorithm to make a decision, it may need tens of microseconds to copy the dataset among sensors/actuators, external memory, and internal memory of CMP [22].
520 $a In this thesis, in order to accelerate the access time between sensors/actuators and processors, we introduce an I/O processing scheme combined with a DMA data prefetching optimization technique. Typically, the I/O data is first placed into main memory which takes many clock cycles to access from processors. In this method, the I/O data is placed directly into SPM which reduces the access time between processor and I/O data. To do this, this approach uses DMA to transfer data between I/O port and on-chip memory. In addition, in this approach, we propose a DMA operation optimization technique to reduce the latency by placing DMA operation initialization on processors' idle time frames.
520 $a The experimental results collected by using benchmark programs and graphs generated by TGFF tool clearly show that the proposed approach improves performance of the system significantly. Based on the normalized performance gains using three to five-core CPSs in our experiment results, our approach brings up to 25% improvement on the average in execution time compared to the traditional I/O data transfer scheme without using DMA optimization technique.
590 $a School code: 1251.
650 4 $a Computer engineering. $3 212944
650 4 $a Computer science. $3 199325
650 4 $a Electrical engineering. $3 454503
690 $a 0464
690 $a 0984
690 $a 0544
710 2 $a University of Houston-Clear Lake. $3 766103
773 0 $t Masters Abstracts International $g 55-05(E).
790 $a 1251
791 $a M.S.
792 $a 2016
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10133515