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Automatic analog IC sizing and optim...

Horta, Nuno.

Automatic analog IC sizing and optimization constrained with PVT corners and layout effects

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Automatic analog IC sizing and optimization constrained with PVT corners and layout effectsby Nuno Lourenco, Ricardo Martins, Nuno Horta.
作者:	Lourenco, Nuno.
其他作者:	Martins, Ricardo.
出版者:	Cham :Springer International Publishing :2017.
面頁冊數:	xxvii, 182 p. :ill. (some col.), digital ;24 cm.
Contained By:	Springer eBooks
標題:	Analog integrated circuitsDesign.
電子資源:	http://dx.doi.org/10.1007/978-3-319-42037-0
ISBN:	9783319420370$q(electronic bk.)

Automatic analog IC sizing and optimization constrained with PVT corners and layout effects
Lourenco, Nuno.

Automatic analog IC sizing and optimization constrained with PVT corners and layout effects[electronic resource] /by Nuno Lourenco, Ricardo Martins, Nuno Horta. - Cham :Springer International Publishing :2017. - xxvii, 182 p. :ill. (some col.), digital ;24 cm.

Introduction -- Previous Works on Automatic Analog IC Sizing -- AIDA-C Architecture -- Multi-Objective Optimization Kernel -- AIDA-C Circuit Sizing Results -- Layout-Aware Circuit Sizing -- AIDA-C Layout-aware Circuit Sizing Results -- Conclusions.

This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit's performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.

ISBN: 9783319420370$q(electronic bk.)

Standard No.: 10.1007/978-3-319-42037-0doiSubjects--Topical Terms:

739062
Analog integrated circuits
--Design.

LC Class. No.: TK7874

Dewey Class. No.: 621.3815

Automatic analog IC sizing and optimization constrained with PVT corners and layout effects
LDR:02467nmm a2200313 a 4500 001 504610
003 DE-He213
005 20160729162335.0
006 m d
007 cr nn 008maaau
008 171030s2017 gw s 0 eng d
020 $a 9783319420370$q(electronic bk.)
020 $a 9783319420363$q(paper)
024 7 $a 10.1007/978-3-319-42037-0 $2 doi
035 $a 978-3-319-42037-0
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7874
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 621.3815 $2 23
090 $a TK7874 $b .L892 2017
100 1 $a Lourenco, Nuno. $3 714244
245 1 0 $a Automatic analog IC sizing and optimization constrained with PVT corners and layout effects $h [electronic resource] / $c by Nuno Lourenco, Ricardo Martins, Nuno Horta.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2017.
300 $a xxvii, 182 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Introduction -- Previous Works on Automatic Analog IC Sizing -- AIDA-C Architecture -- Multi-Objective Optimization Kernel -- AIDA-C Circuit Sizing Results -- Layout-Aware Circuit Sizing -- AIDA-C Layout-aware Circuit Sizing Results -- Conclusions.
520 $a This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit's performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.
650 0 $a Analog integrated circuits $x Design. $3 739062
650 1 4 $a Engineering. $3 210888
650 2 4 $a Circuits and Systems. $3 274416
650 2 4 $a Processor Architectures. $3 274498
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 274412
700 1 $a Martins, Ricardo. $3 769458
700 1 $a Horta, Nuno. $3 714245
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-42037-0
950 $a Engineering (Springer-11647)