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Testing of interposer-based 2.5D int...

Chakrabarty, Krishnendu.

Testing of interposer-based 2.5D integrated circuits

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Testing of interposer-based 2.5D integrated circuitsby Ran Wang, Krishnendu Chakrabarty.
作者:	Wang, Ran.
其他作者:	Chakrabarty, Krishnendu.
出版者:	Cham :Springer International Publishing :2017.
面頁冊數:	xiv, 182 p. :ill. (some col.), digital ;24 cm.
Contained By:	Springer eBooks
標題:	Integrated circuits.
電子資源:	http://dx.doi.org/10.1007/978-3-319-54714-5
ISBN:	9783319547145$q(electronic bk.)

Testing of interposer-based 2.5D integrated circuits
Wang, Ran.

Testing of interposer-based 2.5D integrated circuits[electronic resource] /by Ran Wang, Krishnendu Chakrabarty. - Cham :Springer International Publishing :2017. - xiv, 182 p. :ill. (some col.), digital ;24 cm.

Introduction -- Pre-Bond Testing of the Silicon Interposer -- Post-Bond Scan-based Testing of Interposer Interconnects -- Test Architecture and Test-Path Scheduling -- Built-In Self-Test -- ExTest Scheduling and Optimization -- A Programmable Method for Low-Power Scan Shift in SoC Dies -- Conclusions.

This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay faults; Provides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standard; Discusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC die; Includes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs.

ISBN: 9783319547145$q(electronic bk.)

Standard No.: 10.1007/978-3-319-54714-5doiSubjects--Topical Terms:

190434
Integrated circuits.

LC Class. No.: TK7874

Dewey Class. No.: 621.3815

Testing of interposer-based 2.5D integrated circuits
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