國立高雄大學圖資館 |

語系: 繁體中文

說明(常見問題)

圖資館首頁

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

System reduction for nanoscale IC design

Benner, Peter.

System reduction for nanoscale IC design

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	System reduction for nanoscale IC designedited by Peter Benner.
其他作者:	Benner, Peter.
出版者:	Cham :Springer International Publishing :2017.
面頁冊數:	xi, 197 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
標題:	Integrated circuitsDesign and construction.
電子資源:	http://dx.doi.org/10.1007/978-3-319-07236-4
ISBN:	9783319072364$q(electronic bk.)

System reduction for nanoscale IC design
System reduction for nanoscale IC design[electronic resource] /edited by Peter Benner. - Cham :Springer International Publishing :2017. - xi, 197 p. :ill., digital ;24 cm. - Mathematics in industry,201612-3956 ;. - Mathematics in industry ;16..

Preface -- 1 Model order reduction of integrated circuits in electrical networks: Michael Hinze, Martin Kunkel, Ulrich Matthes, and Morten Vierling -- 2 Element-based model reduction in circuit simulation: Andreas Steinbrecher and Tatjana Stykel -- 3 Reduced Representation of Power Grid Models: Peter Benner and Andre Schneider -- 4 Coupling of numeric/symbolic reduction methods for generating parametrized models of nanoelectronic systems: Oliver Schmidt, Matthias Hauser, and Patrick Lang -- 5 Low-Rank Cholesky Factor Krylov Subspace Methods for Generalized Projected Lyapunov Equations: Matthias Bollhofer and Andre K. Eppler -- Index.

This book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and device simulation for specific tasks in the design cycle. The goal is to develop and compare methods for system reduction in the design of high dimensional nanoelectronic ICs, and to test these methods in the practice of semiconductor development. Six chapters describe the challenges for numerical simulation of nanoelectronic circuits and suggest model reduction methods for constituting equations. These include linear and nonlinear differential equations tailored to circuit equations and drift diffusion equations for semiconductor devices. The performance of these methods is illustrated with numerical experiments using real-world data. Readers will benefit from an up-to-date overview of the latest model reduction methods in computational nanoelectronics.

ISBN: 9783319072364$q(electronic bk.)

Standard No.: 10.1007/978-3-319-07236-4doiSubjects--Topical Terms:

184690
Integrated circuits
--Design and construction.

LC Class. No.: TK7874

Dewey Class. No.: 621.3815

System reduction for nanoscale IC design
LDR:02673nmm a2200337 a 4500 001 517840
003 DE-He213
005 20180117113106.0
006 m d
007 cr nn 008maaau
008 180316s2017 gw s 0 eng d
020 $a 9783319072364$q(electronic bk.)
020 $a 9783319072357$q(paper)
024 7 $a 10.1007/978-3-319-07236-4 $2 doi
035 $a 978-3-319-07236-4
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7874
072 7 $a PDE $2 bicssc
072 7 $a COM014000 $2 bisacsh
072 7 $a MAT003000 $2 bisacsh
082 0 4 $a 621.3815 $2 23
090 $a TK7874 $b .S995 2017
245 0 0 $a System reduction for nanoscale IC design $h [electronic resource] / $c edited by Peter Benner.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2017.
300 $a xi, 197 p. : $b ill., digital ; $c 24 cm.
490 1 $a Mathematics in industry, $x 1612-3956 ; $v 20
505 0 $a Preface -- 1 Model order reduction of integrated circuits in electrical networks: Michael Hinze, Martin Kunkel, Ulrich Matthes, and Morten Vierling -- 2 Element-based model reduction in circuit simulation: Andreas Steinbrecher and Tatjana Stykel -- 3 Reduced Representation of Power Grid Models: Peter Benner and Andre Schneider -- 4 Coupling of numeric/symbolic reduction methods for generating parametrized models of nanoelectronic systems: Oliver Schmidt, Matthias Hauser, and Patrick Lang -- 5 Low-Rank Cholesky Factor Krylov Subspace Methods for Generalized Projected Lyapunov Equations: Matthias Bollhofer and Andre K. Eppler -- Index.
520 $a This book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and device simulation for specific tasks in the design cycle. The goal is to develop and compare methods for system reduction in the design of high dimensional nanoelectronic ICs, and to test these methods in the practice of semiconductor development. Six chapters describe the challenges for numerical simulation of nanoelectronic circuits and suggest model reduction methods for constituting equations. These include linear and nonlinear differential equations tailored to circuit equations and drift diffusion equations for semiconductor devices. The performance of these methods is illustrated with numerical experiments using real-world data. Readers will benefit from an up-to-date overview of the latest model reduction methods in computational nanoelectronics.
650 0 $a Integrated circuits $x Design and construction. $3 184690
650 0 $a Nanoelectronics $x Design and construction. $3 510262
650 1 4 $a Mathematics. $3 184409
650 2 4 $a Computational Science and Engineering. $3 274685
650 2 4 $a Mathematical Modeling and Industrial Mathematics. $3 274070
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 274412
650 2 4 $a Computer-Aided Engineering (CAD, CAE) and Design. $3 274500
650 2 4 $a Algorithms. $3 184661
650 2 4 $a Appl.Mathematics/Computational Methods of Engineering. $3 273758
700 1 $a Benner, Peter. $3 256468
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer eBooks
830 0 $a Mathematics in industry ; $v 16. $3 560066
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-07236-4
950 $a Mathematics and Statistics (Springer-11649)