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Logic synthesis for finite state mac...

Barkalov, Alexander.

Logic synthesis for finite state machines based on linear chains of statesfoundations, recent developments and challenges /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Logic synthesis for finite state machines based on linear chains of statesby Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski.
其他題名:	foundations, recent developments and challenges /
作者:	Barkalov, Alexander.
其他作者:	Titarenko, Larysa.
出版者:	Cham :Springer International Publishing :2018.
面頁冊數:	viii, 225 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
標題:	Sequential machine theory.
電子資源:	http://dx.doi.org/10.1007/978-3-319-59837-6
ISBN:	9783319598376$q(electronic bk.)

Logic synthesis for finite state machines based on linear chains of statesfoundations, recent developments and challenges /
Barkalov, Alexander.

Logic synthesis for finite state machines based on linear chains of statesfoundations, recent developments and challenges /[electronic resource] :by Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski. - Cham :Springer International Publishing :2018. - viii, 225 p. :ill., digital ;24 cm. - Studies in systems, decision and control,v.1132198-4182 ;. - Studies in systems, decision and control ;v.3..

Introduction -- Finite state machines and ﬁeld-programmable gate arrays -- Linear chains in FSMs -- Hardware reduction for Moore UFSMs -- Hardware reduction for Mealy UFSMs -- Hardware reduction for Moore NFSMs -- Hardware reduction for Moore XFSMs.

This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs) To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations) This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation. This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control units.

ISBN: 9783319598376$q(electronic bk.)

Standard No.: 10.1007/978-3-319-59837-6doiSubjects--Topical Terms:

185584
Sequential machine theory.

LC Class. No.: QA267.5.S4

Dewey Class. No.: 511.35

Logic synthesis for finite state machines based on linear chains of statesfoundations, recent developments and challenges /
LDR:02432nmm a2200325 a 4500 001 526564
003 DE-He213
005 20170624084123.0
006 m d
007 cr nn 008maaau
008 181012s2018 gw s 0 eng d
020 $a 9783319598376$q(electronic bk.)
020 $a 9783319598369$q(paper)
024 7 $a 10.1007/978-3-319-59837-6 $2 doi
035 $a 978-3-319-59837-6
040 $a GP $c GP
041 0 $a eng
050 4 $a QA267.5.S4
072 7 $a UYQ $2 bicssc
072 7 $a COM004000 $2 bisacsh
082 0 4 $a 511.35 $2 23
090 $a QA267.5.S4 $b B254 2018
100 1 $a Barkalov, Alexander. $3 285899
245 1 0 $a Logic synthesis for finite state machines based on linear chains of states $h [electronic resource] : $b foundations, recent developments and challenges / $c by Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2018.
300 $a viii, 225 p. : $b ill., digital ; $c 24 cm.
490 1 $a Studies in systems, decision and control, $x 2198-4182 ; $v v.113
505 0 $a Introduction -- Finite state machines and ﬁeld-programmable gate arrays -- Linear chains in FSMs -- Hardware reduction for Moore UFSMs -- Hardware reduction for Mealy UFSMs -- Hardware reduction for Moore NFSMs -- Hardware reduction for Moore XFSMs.
520 $a This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs) To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations) This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation. This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control units.
650 0 $a Sequential machine theory. $3 185584
650 1 4 $a Engineering. $3 210888
650 2 4 $a Computational Intelligence. $3 338479
650 2 4 $a Circuits and Systems. $3 274416
700 1 $a Titarenko, Larysa. $3 285898
700 1 $a Bieganowski, Jacek. $3 799213
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer eBooks
830 0 $a Studies in systems, decision and control ; $v v.3. $3 678532
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-59837-6
950 $a Engineering (Springer-11647)