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High-level estimation and exploratio...

Chattopadhyay, Anupam.

High-level estimation and exploration of reliability for multi-processor system-on-chip

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	High-level estimation and exploration of reliability for multi-processor system-on-chipby Zheng Wang, Anupam Chattopadhyay.
作者:	Wang, Zheng.
其他作者:	Chattopadhyay, Anupam.
出版者:	Singapore :Springer Singapore :2018.
面頁冊數:	xx, 197 p. :ill. (some col.), digital ;24 cm.
Contained By:	Springer eBooks
標題:	Systems on a chip.
電子資源:	http://dx.doi.org/10.1007/978-981-10-1073-6
ISBN:	9789811010736$q(electronic bk.)

High-level estimation and exploration of reliability for multi-processor system-on-chip
Wang, Zheng.

High-level estimation and exploration of reliability for multi-processor system-on-chip[electronic resource] /by Zheng Wang, Anupam Chattopadhyay. - Singapore :Springer Singapore :2018. - xx, 197 p. :ill. (some col.), digital ;24 cm. - Computer architecture and design methodologies,2367-3478. - Computer architecture and design methodologies..

Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook.

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

ISBN: 9789811010736$q(electronic bk.)

Standard No.: 10.1007/978-981-10-1073-6doiSubjects--Topical Terms:

224012
Systems on a chip.

LC Class. No.: TK7895.E42

Dewey Class. No.: 006.22

High-level estimation and exploration of reliability for multi-processor system-on-chip
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