國立高雄大學圖資館 |

語系: 繁體中文

說明(常見問題)

圖資館首頁

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

Low-power design and power-aware ver...

Khondkar, Progyna.

Low-power design and power-aware verification

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Low-power design and power-aware verificationby Progyna Khondkar.
作者:	Khondkar, Progyna.
出版者:	Cham :Springer International Publishing :2018.
面頁冊數:	xv, 155 p. :ill. (some col.), digital ;24 cm.
Contained By:	Springer eBooks
標題:	Low voltage integrated circuitsDesign and construction.
電子資源:	http://dx.doi.org/10.1007/978-3-319-66619-8
ISBN:	9783319666198$q(electronic bk.)

Low-power design and power-aware verification
Khondkar, Progyna.

Low-power design and power-aware verification[electronic resource] /by Progyna Khondkar. - Cham :Springer International Publishing :2018. - xv, 155 p. :ill. (some col.), digital ;24 cm.

1 Introduction -- 2 Background -- 3 Modeling UPF -- 4 Power Aware Standardization of Library -- 5 UPF Based Power Aware Dynamic Simulation -- 6 Power Aware Dynamic Simulation Coverage -- 7 UPF Based Power Aware Static Verification -- 8 References.

Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base. LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF) Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers.

ISBN: 9783319666198$q(electronic bk.)

Standard No.: 10.1007/978-3-319-66619-8doiSubjects--Topical Terms:

184466
Low voltage integrated circuits
--Design and construction.

LC Class. No.: TK7874.66 / .K46 2018

Dewey Class. No.: 621.3815

Low-power design and power-aware verification
LDR:02536nmm a2200313 a 4500 001 528721
003 DE-He213
005 20180620104507.0
006 m d
007 cr nn 008maaau
008 181030s2018 gw s 0 eng d
020 $a 9783319666198$q(electronic bk.)
020 $a 9783319666181$q(paper)
024 7 $a 10.1007/978-3-319-66619-8 $2 doi
035 $a 978-3-319-66619-8
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7874.66 $b .K46 2018
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 621.3815 $2 23
090 $a TK7874.66 $b .K45 2018
100 1 $a Khondkar, Progyna. $3 801326
245 1 0 $a Low-power design and power-aware verification $h [electronic resource] / $c by Progyna Khondkar.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2018.
300 $a xv, 155 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a 1 Introduction -- 2 Background -- 3 Modeling UPF -- 4 Power Aware Standardization of Library -- 5 UPF Based Power Aware Dynamic Simulation -- 6 Power Aware Dynamic Simulation Coverage -- 7 UPF Based Power Aware Static Verification -- 8 References.
520 $a Until now, there has been a lack of a complete knowledge base to fully comprehend Low power (LP) design and power aware (PA) verification techniques and methodologies and deploy them all together in a real design verification and implementation project. This book is a first approach to establishing a comprehensive PA knowledge base. LP design, PA verification, and Unified Power Format (UPF) or IEEE-1801 power format standards are no longer special features. These technologies and methodologies are now part of industry-standard design, verification, and implementation flows (DVIF) Almost every chip design today incorporates some kind of low power technique either through power management on chip, by dividing the design into different voltage areas and controlling the voltages, through PA dynamic and PA static verification, or their combination. The entire LP design and PA verification process involves thousands of techniques, tools, and methodologies, employed from the r egister transfer level (RTL) of design abstraction down to the synthesis or place-and-route levels of physical design. These techniques, tools, and methodologies are evolving everyday through the progression of design-verification complexity and more intelligent ways of handling that complexity by engineers, researchers, and corporate engineering policy makers.
650 0 $a Low voltage integrated circuits $x Design and construction. $3 184466
650 1 4 $a Engineering. $3 210888
650 2 4 $a Circuits and Systems. $3 274416
650 2 4 $a Software Engineering. $3 274511
650 2 4 $a Processor Architectures. $3 274498
650 2 4 $a Performance and Reliability. $3 277564
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-66619-8
950 $a Engineering (Springer-11647)