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Fault tolerant architectures for cry...

Mukhopadhyay, Debdeep.

Fault tolerant architectures for cryptography and hardware security

Record Type:	Electronic resources : Monograph/item
Title/Author:	Fault tolerant architectures for cryptography and hardware securityedited by Sikhar Patranabis, Debdeep Mukhopadhyay.
other author:	Patranabis, Sikhar.
Published:	Singapore :Springer Singapore :2018.
Description:	xii, 240 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
Subject:	Fault-tolerant computing.
Online resource:	http://dx.doi.org/10.1007/978-981-10-1387-4
ISBN:	9789811013874$q(electronic bk.)

Fault tolerant architectures for cryptography and hardware security
Fault tolerant architectures for cryptography and hardware security[electronic resource] /edited by Sikhar Patranabis, Debdeep Mukhopadhyay. - Singapore :Springer Singapore :2018. - xii, 240 p. :ill., digital ;24 cm. - Computer architecture and design methodologies,2367-3478. - Computer architecture and design methodologies..

Introduction to Fault Analysis -- Classical Fault Analysis -- Recent Trends and Advances in Fault Analysis -- Automation of Fault Analysis -- Countermeasures and Fault Tolerant Architectures -- Practical Perspectives of Fault Tolerant Design.

This book uses motivating examples and real-life attack scenarios to introduce readers to the general concept of fault attacks in cryptography. It offers insights into how the fault tolerance theories developed in the book can actually be implemented, with a particular focus on a wide spectrum of fault models and practical fault injection techniques, ranging from simple, low-cost techniques to high-end equipment-based methods. It then individually examines fault attack vulnerabilities in symmetric, asymmetric and authenticated encryption systems. This is followed by extensive coverage of countermeasure techniques and fault tolerant architectures that attempt to thwart such vulnerabilities. Lastly, it presents a case study of a comprehensive FPGA-based fault tolerant architecture for AES-128, which brings together of a number of the fault tolerance techniques presented. It concludes with a discussion on how fault tolerance can be combined with side channel security to achieve protection against implementation-based attacks. The text is supported by illustrative diagrams, algorithms, tables and diagrams presenting real-world experimental results.

ISBN: 9789811013874$q(electronic bk.)

Standard No.: 10.1007/978-981-10-1387-4doiSubjects--Topical Terms:

324957
Fault-tolerant computing.

LC Class. No.: QA76.9.F38 / F385 2018

Dewey Class. No.: 005.1

Fault tolerant architectures for cryptography and hardware security
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245 0 0 $a Fault tolerant architectures for cryptography and hardware security $h [electronic resource] / $c edited by Sikhar Patranabis, Debdeep Mukhopadhyay.
260 $a Singapore : $b Springer Singapore : $b Imprint: Springer, $c 2018.
300 $a xii, 240 p. : $b ill., digital ; $c 24 cm.
490 1 $a Computer architecture and design methodologies, $x 2367-3478
505 0 $a Introduction to Fault Analysis -- Classical Fault Analysis -- Recent Trends and Advances in Fault Analysis -- Automation of Fault Analysis -- Countermeasures and Fault Tolerant Architectures -- Practical Perspectives of Fault Tolerant Design.
520 $a This book uses motivating examples and real-life attack scenarios to introduce readers to the general concept of fault attacks in cryptography. It offers insights into how the fault tolerance theories developed in the book can actually be implemented, with a particular focus on a wide spectrum of fault models and practical fault injection techniques, ranging from simple, low-cost techniques to high-end equipment-based methods. It then individually examines fault attack vulnerabilities in symmetric, asymmetric and authenticated encryption systems. This is followed by extensive coverage of countermeasure techniques and fault tolerant architectures that attempt to thwart such vulnerabilities. Lastly, it presents a case study of a comprehensive FPGA-based fault tolerant architecture for AES-128, which brings together of a number of the fault tolerance techniques presented. It concludes with a discussion on how fault tolerance can be combined with side channel security to achieve protection against implementation-based attacks. The text is supported by illustrative diagrams, algorithms, tables and diagrams presenting real-world experimental results.
650 0 $a Fault-tolerant computing. $3 324957
650 0 $a Computer security. $3 184416
650 1 4 $a Engineering. $3 210888
650 2 4 $a Circuits and Systems. $3 274416
650 2 4 $a Data Encryption. $3 273765
650 2 4 $a Security Science and Technology. $3 510148
700 1 $a Patranabis, Sikhar. $3 809612
700 1 $a Mukhopadhyay, Debdeep. $3 535778
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer eBooks
830 0 $a Computer architecture and design methodologies. $3 753537
856 4 0 $u http://dx.doi.org/10.1007/978-981-10-1387-4
950 $a Engineering (Springer-11647)