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Design on High Performance Nanoscale...

University of Nevada, Las Vegas.

Design on High Performance Nanoscale CMOS Circuits with Low Temperature Sensitivity.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Design on High Performance Nanoscale CMOS Circuits with Low Temperature Sensitivity.
作者:	Zhu, Ming.
出版者:	Ann Arbor : ProQuest Dissertations & Theses, 2018
面頁冊數:	108 p.
附註:	Source: Dissertation Abstracts International, Volume: 80-02(E), Section: B.
附註:	Adviser: Yingtao Jiang.
Contained By:	Dissertation Abstracts International80-02B(E).
標題:	Electrical engineering.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10219592
ISBN:	9780438459274

Design on High Performance Nanoscale CMOS Circuits with Low Temperature Sensitivity.
Zhu, Ming.

Design on High Performance Nanoscale CMOS Circuits with Low Temperature Sensitivity. - Ann Arbor : ProQuest Dissertations & Theses, 2018 - 108 p.

Source: Dissertation Abstracts International, Volume: 80-02(E), Section: B.

Thesis (Ph.D.)--University of Nevada, Las Vegas, 2018.

With the rapid development of integrated circuit (IC) design and manufacturing technology, the transistor size now can be shrunk into only couple of nanometers whereas billions of transistors can be squeezed into a square millimeter, providing unprecedented computation power. However, accompanied with continuous device miniaturization and increased integration density is the explosive growth of on-chip power dissipation and a wide range of temperature fluctuation, which can heavily and negatively affect the delay performance of the circuit, or in the worst case, the circuit may malfunction and the system can be unreliable. Therefore, improved performance resilience against temperature variations has become one of the key requirements for nanoscale VLSI circuit designs.

ISBN: 9780438459274Subjects--Topical Terms:

454503
Electrical engineering.

Design on High Performance Nanoscale CMOS Circuits with Low Temperature Sensitivity.
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300 $a 108 p.
500 $a Source: Dissertation Abstracts International, Volume: 80-02(E), Section: B.
500 $a Adviser: Yingtao Jiang.
502 $a Thesis (Ph.D.)--University of Nevada, Las Vegas, 2018.
520 $a With the rapid development of integrated circuit (IC) design and manufacturing technology, the transistor size now can be shrunk into only couple of nanometers whereas billions of transistors can be squeezed into a square millimeter, providing unprecedented computation power. However, accompanied with continuous device miniaturization and increased integration density is the explosive growth of on-chip power dissipation and a wide range of temperature fluctuation, which can heavily and negatively affect the delay performance of the circuit, or in the worst case, the circuit may malfunction and the system can be unreliable. Therefore, improved performance resilience against temperature variations has become one of the key requirements for nanoscale VLSI circuit designs.
520 $a In this dissertation, we first survey the literature and run simulations of a single logic gate to illustrate how temperature affects the circuit delay, and determine the key factors that can influence the circuit performance. Next, we will discuss the existing circuit techniques to address thermal issues in nanoscale electronics. Our research shows that high speed temperature-insensitive CMOS logic circuit designs can be achieved with two techniques: 1) using a temperature adaptive power supply to power the logic circuit, and 2) employing logic structures built upon logic gates with small fan-ins (≤ 4) and shorter logic paths. A power supply that is adaptive to temperature variation can be adopted that any performance loss due to the increase of temperature can be compensated by the increase of supply voltage. This observation leads us to propose a CTAT-like temperature adaptive voltage power supply, and adopting this power supply will free designers from using otherwise expensive on-chip temperature sensors, as the case in traditional temperature related power management modules. We also propose a logic synthesis algorithm that maps a general Boolean function to a real logic circuit, with smaller fan-ins and shorter logic paths for low delay and thermal-induced delay variations.
520 $a Experiments on various benchmark circuits, implemented with a 45nm CMOS technology, have confirmed that, when a single constant power supply is employed, both absolute circuit delays and temperature-induced delay variations can be reduced by more than 20% as the circuits are implemented using logic gates with small fan-ins and short logic paths. When a CTAT-like adaptive voltage supply is included to power the circuit, in replacement of a single fixed power source, the same circuits will experience even smaller delay variations, in the range of 15%&sim;30% for temperature varies between 0° and 90°, a sharp contrast to 60%&sim;100% delay variations observed in large fan-in logic circuits powered by a single constant power supply.
590 $a School code: 0506.
650 4 $a Electrical engineering. $3 454503
650 4 $a Computer engineering. $3 212944
650 4 $a Computer science. $3 199325
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710 2 $a University of Nevada, Las Vegas. $b Electrical and Computer Engineering. $3 795327
773 0 $t Dissertation Abstracts International $g 80-02B(E).
790 $a 0506
791 $a Ph.D.
792 $a 2018
793 $a English
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=10219592