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Digital subsampling phase lock techn...

Markulic, Nereo.

Digital subsampling phase lock techniques for frequency synthesis and polar transmission

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Digital subsampling phase lock techniques for frequency synthesis and polar transmissionby Nereo Markulic ... [et al.].
其他作者:	Markulic, Nereo.
出版者:	Cham :Springer International Publishing :2019.
面頁冊數:	xxiii, 138 p. :ill. (some col.), digital ;24 cm.
Contained By:	Springer eBooks
標題:	Phase-locked loops.
電子資源:	https://doi.org/10.1007/978-3-030-10958-5
ISBN:	9783030109585$q(electronic bk.)

Digital subsampling phase lock techniques for frequency synthesis and polar transmission
Digital subsampling phase lock techniques for frequency synthesis and polar transmission[electronic resource] /by Nereo Markulic ... [et al.]. - Cham :Springer International Publishing :2019. - xxiii, 138 p. :ill. (some col.), digital ;24 cm. - Analog circuits and signal processing,1872-082X. - Analog circuits and signal processing..

Chapter 1. Introduction -- Chapter 2. A Digital-to-Time Converter based Subsampling PLL for Fractional Synthesis -- Chapter 3. A Background-Calibrated Subsampling PLL for Phase/Frequency Modulation -- Chapter 4. A Background-Calibrated Digital Subsampling Polar Transmitter -- Chapter 5. Conclusion and Future Outlook.

This book explains concepts behind fractional subsampling-based frequency synthesis that is re-shaping today's art in the field of low-noise LO generation. It covers advanced material, giving clear guidance for development of background-calibrated environments capable of spur-free synthesis and wideband phase modulation. It further expands the concepts into the field of subsampling polar transmission, where the newly developed architecture enables unprecedented spectral efficiency levels, unquestionably required by the upcoming generation of wireless standards. Guides development of DTC-based Fractional-N Subsampling PLL and Subsampling Polar Transmitters, covering material from fundamental theory, over system level considerations to building block IC implementation; Describes a fully background-calibrated environment that can used in general context of fractional frequency synthesis and/or phase/frequency modulation; Presents three IC implementations, showing system level analysis, design methodology, circuit details and measurement results.

ISBN: 9783030109585$q(electronic bk.)

Standard No.: namm 22003373 a 450Subjects--Topical Terms:

182354
Phase-locked loops.

LC Class. No.: TK7872.P38

Dewey Class. No.: 621.3815364

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245 0 0 $a Digital subsampling phase lock techniques for frequency synthesis and polar transmission $h [electronic resource] / $c by Nereo Markulic ... [et al.].
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490 1 $a Analog circuits and signal processing, $x 1872-082X
505 0 $a Chapter 1. Introduction -- Chapter 2. A Digital-to-Time Converter based Subsampling PLL for Fractional Synthesis -- Chapter 3. A Background-Calibrated Subsampling PLL for Phase/Frequency Modulation -- Chapter 4. A Background-Calibrated Digital Subsampling Polar Transmitter -- Chapter 5. Conclusion and Future Outlook.
520 $a This book explains concepts behind fractional subsampling-based frequency synthesis that is re-shaping today's art in the field of low-noise LO generation. It covers advanced material, giving clear guidance for development of background-calibrated environments capable of spur-free synthesis and wideband phase modulation. It further expands the concepts into the field of subsampling polar transmission, where the newly developed architecture enables unprecedented spectral efficiency levels, unquestionably required by the upcoming generation of wireless standards. Guides development of DTC-based Fractional-N Subsampling PLL and Subsampling Polar Transmitters, covering material from fundamental theory, over system level considerations to building block IC implementation; Describes a fully background-calibrated environment that can used in general context of fractional frequency synthesis and/or phase/frequency modulation; Presents three IC implementations, showing system level analysis, design methodology, circuit details and measurement results.
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