國立高雄大學圖資館 |

語系: 繁體中文

說明(常見問題)

圖資館首頁

登入

回首頁

切換: 標籤 | MARC模式 | ISBD

System-on-chip securityvalidation an...

Farahmandi, Farimah.

System-on-chip securityvalidation and verification /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	System-on-chip securityby Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra.
其他題名:	validation and verification /
作者:	Farahmandi, Farimah.
其他作者:	Huang, Yuanwen.
出版者:	Cham :Springer International Publishing :2020.
面頁冊數:	xix, 289 p. :ill. (some col.), digital ;24 cm.
Contained By:	Springer eBooks
標題:	Systems on a chipSecurity measures.
電子資源:	https://doi.org/10.1007/978-3-030-30596-3
ISBN:	9783030305963$q(electronic bk.)

System-on-chip securityvalidation and verification /
Farahmandi, Farimah.

System-on-chip securityvalidation and verification /[electronic resource] :by Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra. - Cham :Springer International Publishing :2020. - xix, 289 p. :ill. (some col.), digital ;24 cm.

Introduction -- Security Verification Using Formal Methods -- Simulation-Based Security Validation Approaches -- Security Validation Using Side-Channel Analysis -- Automated Vulnerability Detection And Mitigation -- Conclusion.

This book describes a wide variety of System-on-Chip (SoC) security threats and vulnerabilities, as well as their sources, in each stage of a design life cycle. The authors discuss a wide variety of state-of-the-art security verification and validation approaches such as formal methods and side-channel analysis, as well as simulation-based security and trust validation approaches. This book provides a comprehensive reference for system on chip designers and verification and validation engineers interested in verifying security and trust of heterogeneous SoCs. Outlines a wide variety of hardware security threats and vulnerabilities as well as their sources in each of the stages of a design life cycle; Summarizes unsafe current design practices that lead to security and trust vulnerabilities; Covers state-of-the-art techniques as well as ongoing research efforts in developing scalable security validation using formal methods including symbolic algebra, model checkers, SAT solvers, and theorem provers; Explains how to leverage security validation approaches to prevent side-channel attacks; Presents automated debugging and patching techniques in the presence of security vulnerabilities; Includes case studies for security validation of arithmetic circuits, controller designs, as well as processor-based SoCs.

ISBN: 9783030305963$q(electronic bk.)

Standard No.: 10.1007/978-3-030-30596-3doiSubjects--Topical Terms:

834369
Systems on a chip
--Security measures.

LC Class. No.: TK7895.E42 / F373 2020

Dewey Class. No.: 006.22

System-on-chip securityvalidation and verification /
LDR:02561nmm a2200325 a 4500 001 574120
003 DE-He213
005 20200312150446.0
006 m d
007 cr nn 008maaau
008 201007s2020 sz s 0 eng d
020 $a 9783030305963$q(electronic bk.)
020 $a 9783030305956$q(paper)
024 7 $a 10.1007/978-3-030-30596-3 $2 doi
035 $a 978-3-030-30596-3
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7895.E42 $b F373 2020
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 006.22 $2 23
090 $a TK7895.E42 $b F219 2020
100 1 $a Farahmandi, Farimah. $3 830728
245 1 0 $a System-on-chip security $h [electronic resource] : $b validation and verification / $c by Farimah Farahmandi, Yuanwen Huang, Prabhat Mishra.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2020.
300 $a xix, 289 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Introduction -- Security Verification Using Formal Methods -- Simulation-Based Security Validation Approaches -- Security Validation Using Side-Channel Analysis -- Automated Vulnerability Detection And Mitigation -- Conclusion.
520 $a This book describes a wide variety of System-on-Chip (SoC) security threats and vulnerabilities, as well as their sources, in each stage of a design life cycle. The authors discuss a wide variety of state-of-the-art security verification and validation approaches such as formal methods and side-channel analysis, as well as simulation-based security and trust validation approaches. This book provides a comprehensive reference for system on chip designers and verification and validation engineers interested in verifying security and trust of heterogeneous SoCs. Outlines a wide variety of hardware security threats and vulnerabilities as well as their sources in each of the stages of a design life cycle; Summarizes unsafe current design practices that lead to security and trust vulnerabilities; Covers state-of-the-art techniques as well as ongoing research efforts in developing scalable security validation using formal methods including symbolic algebra, model checkers, SAT solvers, and theorem provers; Explains how to leverage security validation approaches to prevent side-channel attacks; Presents automated debugging and patching techniques in the presence of security vulnerabilities; Includes case studies for security validation of arithmetic circuits, controller designs, as well as processor-based SoCs.
650 0 $a Systems on a chip $x Security measures. $3 834369
650 0 $a Systems on a chip $x Design. $3 456731
650 1 4 $a Circuits and Systems. $3 274416
650 2 4 $a Processor Architectures. $3 274498
650 2 4 $a Electronics and Microelectronics, Instrumentation. $3 274412
700 1 $a Huang, Yuanwen. $3 861689
700 1 $a Mishra, Prabhat. $3 253937
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer eBooks
856 4 0 $u https://doi.org/10.1007/978-3-030-30596-3
950 $a Engineering (Springer-11647)