Language:
English
繁體中文
Help
圖資館首頁
Login
Back
Switch To:
Labeled
|
MARC Mode
|
ISBD
In-memory computingsynthesis and opt...
~
Drechsler, Rolf.
In-memory computingsynthesis and optimization /
Record Type:
Electronic resources : Monograph/item
Title/Author:
In-memory computingby Saeideh Shirinzadeh, Rolf Drechsler.
Reminder of title:
synthesis and optimization /
Author:
Shirinzadeh, Saeideh.
other author:
Drechsler, Rolf.
Published:
Cham :Springer International Publishing :2020.
Description:
xi, 115 p. :ill., digital ;24 cm.
Contained By:
Springer eBooks
Subject:
Computer storage devices.
Online resource:
https://doi.org/10.1007/978-3-030-18026-3
ISBN:
9783030180263$q(electronic bk.)
In-memory computingsynthesis and optimization /
Shirinzadeh, Saeideh.
In-memory computing
synthesis and optimization /[electronic resource] :by Saeideh Shirinzadeh, Rolf Drechsler. - Cham :Springer International Publishing :2020. - xi, 115 p. :ill., digital ;24 cm.
Chapter 1: Introduction -- Chapter 2: Background -- Chapter 3: BDD Optimization and Approximation: A Multi-Criteria Approach -- Chapter 4: Synthesis for Logic-in-Memory Computing using RRAM -- Chapter 5: Compilation and Wear Le0veling for Programmable Logic-in-Memory (PLiM) Architecture -- Chapter 6: Conclusions.
This book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime. Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing; Describes automated compilation of programmable logic-in-memory computer architectures; Includes several effective optimization algorithm also applicable to classical logic synthesis; Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it.
ISBN: 9783030180263$q(electronic bk.)
Standard No.: 10.1007/978-3-030-18026-3doiSubjects--Topical Terms:
202780
Computer storage devices.
LC Class. No.: TK7895.M4
Dewey Class. No.: 004.5
In-memory computingsynthesis and optimization /
LDR
:02316nmm a2200325 a 4500
001
577994
003
DE-He213
005
20200211132728.0
006
m d
007
cr nn 008maaau
008
201208s2020 sz s 0 eng d
020
$a
9783030180263$q(electronic bk.)
020
$a
9783030180256$q(paper)
024
7
$a
10.1007/978-3-030-18026-3
$2
doi
035
$a
978-3-030-18026-3
040
$a
GP
$c
GP
041
0
$a
eng
050
4
$a
TK7895.M4
072
7
$a
TJFC
$2
bicssc
072
7
$a
TEC008010
$2
bisacsh
072
7
$a
TJFC
$2
thema
082
0 4
$a
004.5
$2
23
090
$a
TK7895.M4
$b
S558 2020
100
1
$a
Shirinzadeh, Saeideh.
$3
866617
245
1 0
$a
In-memory computing
$h
[electronic resource] :
$b
synthesis and optimization /
$c
by Saeideh Shirinzadeh, Rolf Drechsler.
260
$a
Cham :
$b
Springer International Publishing :
$b
Imprint: Springer,
$c
2020.
300
$a
xi, 115 p. :
$b
ill., digital ;
$c
24 cm.
505
0
$a
Chapter 1: Introduction -- Chapter 2: Background -- Chapter 3: BDD Optimization and Approximation: A Multi-Criteria Approach -- Chapter 4: Synthesis for Logic-in-Memory Computing using RRAM -- Chapter 5: Compilation and Wear Le0veling for Programmable Logic-in-Memory (PLiM) Architecture -- Chapter 6: Conclusions.
520
$a
This book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime. Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing; Describes automated compilation of programmable logic-in-memory computer architectures; Includes several effective optimization algorithm also applicable to classical logic synthesis; Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it.
650
0
$a
Computer storage devices.
$3
202780
650
0
$a
Nonvolatile random-access memory.
$3
680408
650
1 4
$a
Circuits and Systems.
$3
274416
650
2 4
$a
Processor Architectures.
$3
274498
650
2 4
$a
Electronics and Microelectronics, Instrumentation.
$3
274412
700
1
$a
Drechsler, Rolf.
$3
253914
710
2
$a
SpringerLink (Online service)
$3
273601
773
0
$t
Springer eBooks
856
4 0
$u
https://doi.org/10.1007/978-3-030-18026-3
950
$a
Engineering (Springer-11647)
based on 0 review(s)
ALL
電子館藏
Items
1 records • Pages 1 •
1
Inventory Number
Location Name
Item Class
Material type
Call number
Usage Class
Loan Status
No. of reservations
Opac note
Attachments
000000182892
電子館藏
1圖書
電子書
EB TK7895.M4 S558 2020 2020
一般使用(Normal)
On shelf
0
1 records • Pages 1 •
1
Multimedia
Multimedia file
https://doi.org/10.1007/978-3-030-18026-3
Reviews
Add a review
and share your thoughts with other readers
Export
pickup library
Processing
...
Change password
Login