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SoC physical designa comprehensive guide /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	SoC physical designby Veena S. Chakravarthi, Shivananda R. Koteshwar.
其他題名:	a comprehensive guide /
作者:	Chakravarthi, Veena S.
其他作者:	Koteshwar, Shivananda R.
出版者:	Cham :Springer International Publishing :2022.
面頁冊數:	xxiv, 155 p. :ill., digital ;24 cm.
Contained By:	Springer Nature eBook
標題:	Systems on a chip.
電子資源:	https://doi.org/10.1007/978-3-030-98112-9
ISBN:	9783030981129$q(electronic bk.)

SoC physical designa comprehensive guide /
Chakravarthi, Veena S.

SoC physical designa comprehensive guide /[electronic resource] :by Veena S. Chakravarthi, Shivananda R. Koteshwar. - Cham :Springer International Publishing :2022. - xxiv, 155 p. :ill., digital ;24 cm.

Introduction -- SoC Physical Design Flow and Algorithms -- Physical Design Floor Plan and Placement -- Clock, Reset, and HFN -- Physical Design Routing -- Physical Design Verification.

SoC Physical Design is a comprehensive practical guide for VLSI designers that thoroughly examines and explains the practical physical design flow of system on chip (SoC) The book covers the rationale behind making design decisions on power, performance, and area (PPA) goals for SoC and explains the required design environment algorithms, design flows, constraints, handoff procedures, and design infrastructure requirements in achieving them. The book reveals challenges likely to be faced at each design process and ways to address them in practical design environments. Advanced topics on 3D ICs, EDA trends, and SOC trends are discussed in later chapters. Coverage also includes advanced physical design techniques followed for deep submicron SOC designs. The book provides aspiring VLSI designers, practicing design engineers, and electrical engineering students with a solid background on the complex physical design requirements of SoCs which are required to contribute effectively in design roles. Provides a comprehensive overview of the skills required for complex SoC design and development; Examines SOC design challenges in nanotechnology scales; Offers readers professional "tricks" to using tools for optimal design runs.

ISBN: 9783030981129$q(electronic bk.)

Standard No.: 10.1007/978-3-030-98112-9doiSubjects--Topical Terms:

224012
Systems on a chip.

LC Class. No.: TK7895.E42 / C43 2022

Dewey Class. No.: 621.3815

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