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Built-in fault-tolerant computing paradigm for resilient large-scale chip designa self-test, self-diagnosis, and self-repair-based approach /

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Built-in fault-tolerant computing paradigm for resilient large-scale chip designby Xiaowei Li, Guihai Yan, Cheng Liu.
其他題名:	a self-test, self-diagnosis, and self-repair-based approach /
作者:	Li, Xiaowei.
其他作者:	Yan, Guihai.
出版者:	Singapore :Springer Nature Singapore :2023.
面頁冊數:	xviii, 304 p. :ill., digital ;24 cm.
Contained By:	Springer Nature eBook
標題:	Integrated circuitsLarge scale integration
電子資源:	https://doi.org/10.1007/978-981-19-8551-5
ISBN:	9789811985515$q(electronic bk.)

Built-in fault-tolerant computing paradigm for resilient large-scale chip designa self-test, self-diagnosis, and self-repair-based approach /
Li, Xiaowei.

Built-in fault-tolerant computing paradigm for resilient large-scale chip designa self-test, self-diagnosis, and self-repair-based approach /[electronic resource] :by Xiaowei Li, Guihai Yan, Cheng Liu. - Singapore :Springer Nature Singapore :2023. - xviii, 304 p. :ill., digital ;24 cm.

Chapter 1: Introduction -- Chapter 2: Fault-tolerant general circuits with 3S -- Chapter 3: Fault-tolerant general purposed processors with 3S -- Chapter 4: Fault-tolerant network-on-chip with 3S -- Chapter 5: Fault-tolerant deep learning processors with 3S -- Chapter 6: Conclusion.

With the end of Dennard scaling and Moore's law, IC chips, especially large-scale ones, now face more reliability challenges, and reliability has become one of the mainstay merits of VLSI designs. In this context, this book presents a built-in on-chip fault-tolerant computing paradigm that seeks to combine fault detection, fault diagnosis, and error recovery in large-scale VLSI design in a unified manner so as to minimize resource overhead and performance penalties. Following this computing paradigm, we propose a holistic solution based on three key components: self-test, self-diagnosis and self-repair, or "3S" for short. We then explore the use of 3S for general IC designs, general-purpose processors, network-on-chip (NoC) and deep learning accelerators, and present prototypes to demonstrate how 3S responds to in-field silicon degradation and recovery under various runtime faults caused by aging, process variations, or radical particles. Moreover, we demonstrate that 3S not only offers a powerful backbone for various on-chip fault-tolerant designs and implementations, but also has farther-reaching implications such as maintaining graceful performance degradation, mitigating the impact of verification blind spots, and improving chip yield. This book is the outcome of extensive fault-tolerant computing research pursued at the State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences over the past decade. The proposed built-in on-chip fault-tolerant computing paradigm has been verified in a broad range of scenarios, from small processors in satellite computers to large processors in HPCs. Hopefully, it will provide an alternative yet effective solution to the growing reliability challenges for large-scale VLSI designs.

ISBN: 9789811985515$q(electronic bk.)

Standard No.: 10.1007/978-981-19-8551-5doiSubjects--Topical Terms:

946176
Integrated circuits
--Large scale integration

LC Class. No.: TK7874

Dewey Class. No.: 621.395

Built-in fault-tolerant computing paradigm for resilient large-scale chip designa self-test, self-diagnosis, and self-repair-based approach /
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