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Design and analysis of scalable floa...

Montano Martinez, Victor Brian.

Design and analysis of scalable floating point fast Fourier transforms on field programmable gate arrays.

Record Type:	Electronic resources : Monograph/item
Title/Author:	Design and analysis of scalable floating point fast Fourier transforms on field programmable gate arrays.
Author:	Montano Martinez, Victor Brian.
Description:	120 p.
Notes:	Source: Masters Abstracts International, Volume: 48-02, page: .
Notes:	Adviser: Manuel Jimenez.
Contained By:	Masters Abstracts International48-02.
Subject:	Engineering, Electronics and Electrical.
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=1471661
ISBN:	9781109445152

Design and analysis of scalable floating point fast Fourier transforms on field programmable gate arrays.
Montano Martinez, Victor Brian.

Design and analysis of scalable floating point fast Fourier transforms on field programmable gate arrays. - 120 p.

Source: Masters Abstracts International, Volume: 48-02, page: .

Thesis (M.S.)--University of Puerto Rico, Mayaguez (Puerto Rico), 2010.

This project analyzed the impact on the performance of a floating point Fast Fourier Transform (FFT) of modifying design parameters that included the number of points, precision, and folding factor. The performance parameters observed included the latency, resource consumption, maximum clock frequency, and throughput. In order to complete this study, a scalable core of a floating point FFT was designed using a Hardware Description Language (HDL) and implemented on a Xilinx Virtex IV Field Programmable Gate Array (FPGA). The FFT design was structured to allow for scaling the number of points, the number of bits in operands, the folding factor, and the transform direction, either forward or reverse. The behavior of the latency and throughput could be predicted with a set of empirical formulas derived from the design. The resources consumed and maximum frequency provided a good understanding of the effects caused by each generic parameter on the design performance.

ISBN: 9781109445152Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Design and analysis of scalable floating point fast Fourier transforms on field programmable gate arrays.
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245 1 0 $a Design and analysis of scalable floating point fast Fourier transforms on field programmable gate arrays.
300 $a 120 p.
500 $a Source: Masters Abstracts International, Volume: 48-02, page: .
500 $a Adviser: Manuel Jimenez.
502 $a Thesis (M.S.)--University of Puerto Rico, Mayaguez (Puerto Rico), 2010.
520 $a This project analyzed the impact on the performance of a floating point Fast Fourier Transform (FFT) of modifying design parameters that included the number of points, precision, and folding factor. The performance parameters observed included the latency, resource consumption, maximum clock frequency, and throughput. In order to complete this study, a scalable core of a floating point FFT was designed using a Hardware Description Language (HDL) and implemented on a Xilinx Virtex IV Field Programmable Gate Array (FPGA). The FFT design was structured to allow for scaling the number of points, the number of bits in operands, the folding factor, and the transform direction, either forward or reverse. The behavior of the latency and throughput could be predicted with a set of empirical formulas derived from the design. The resources consumed and maximum frequency provided a good understanding of the effects caused by each generic parameter on the design performance.
590 $a School code: 0553.
650 4 $a Engineering, Electronics and Electrical. $3 226981
690 $a 0544
710 2 $a University of Puerto Rico, Mayaguez (Puerto Rico). $3 384374
773 0 $t Masters Abstracts International $g 48-02.
790 1 0 $a Jimenez, Manuel, $e advisor
790 $a 0553
791 $a M.S.
792 $a 2010
856 4 0 $u http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=1471661