國立高雄大學圖資館 |

語系: 繁體中文

說明(常見問題)

圖資館首頁

登入

回首頁 到查詢結果 [ subject:"Processor Architectures." ]

切換: 標籤 | MARC模式 | ISBD

Introduction to SystemVerilog

Mehta, Ashok B.

Introduction to SystemVerilog

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Introduction to SystemVerilogby Ashok B. Mehta.
作者:	Mehta, Ashok B.
出版者:	Cham :Springer International Publishing :2021.
面頁冊數:	xxxv, 852 p. :ill., digital ;24 cm.
Contained By:	Springer Nature eBook
標題:	SystemVerilog (Computer hardware description language)
電子資源:	https://doi.org/10.1007/978-3-030-71319-5
ISBN:	9783030713195$q(electronic bk.)

Introduction to SystemVerilog
Mehta, Ashok B.

Introduction to SystemVerilog[electronic resource] /by Ashok B. Mehta. - Cham :Springer International Publishing :2021. - xxxv, 852 p. :ill., digital ;24 cm.

Introduction -- Data Types -- Arrays -- Queues -- Structures -- Packages -- Class -- SystemVerilog 'module' -- SystemVerilog 'program' -- Interfaces -- Operators -- Constrained Random Test Generation and Verification -- SystemVerilog Assertions -- Functional Coverage -- SystemVerilog Processes -- Procedural programming statements -- Processes -- Tasks and Functions -- Clocking Blocks -- Checkers -- Inter-process communication and synchronization -- Utility System tasks and functions.

This book provides a hands-on, application-oriented guide to the entire IEEE standard 1800 SystemVerilog language. Readers will benefit from the step-by-step approach to learning the language and methodology nuances, which will enable them to design and verify complex ASIC/SoC and CPU chips. The author covers the entire spectrum of the language, including random constraints, SystemVerilog Assertions, Functional Coverage, Class, checkers, interfaces, and Data Types, among other features of the language. Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the complex task of multi-million gate ASIC designs. Provides comprehensive coverage of the entire IEEE standard SystemVerilog language; Covers important topics such as constrained random verification, SystemVerilog Class, Assertions, Functional coverage, data types, checkers, interfaces, processes and procedures, among other language features; Uses easy to understand examples and simulation logs; examples are simulatable and will be provided online; Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs. This is quite a comprehensive work. It must have taken a long time to write it. I really like that the author has taken apart each of the SystemVerilog constructs and talks about them in great detail, including example code and simulation logs. For example, there is a chapter dedicated to arrays, and another dedicated to queues - that is great to have! The Language Reference Manual (LRM) is quite dense and difficult to use as a text for learning the language. This book explains semantics at a level of detail that is not possible in an LRM. This is the strength of the book. This will be an excellent book for novice users and as a handy reference for experienced programmers. Mark Glasser Cerebras Systems.

ISBN: 9783030713195$q(electronic bk.)

Standard No.: 10.1007/978-3-030-71319-5doiSubjects--Topical Terms:

670683
SystemVerilog (Computer hardware description language)

LC Class. No.: TK7885.7

Dewey Class. No.: 621.392

Introduction to SystemVerilog
LDR:03430nmm a2200325 a 4500 001 602316
003 DE-He213
005 20210707191622.0
006 m d
007 cr nn 008maaau
008 211112s2021 sz s 0 eng d
020 $a 9783030713195$q(electronic bk.)
020 $a 9783030713188$q(paper)
024 7 $a 10.1007/978-3-030-71319-5 $2 doi
035 $a 978-3-030-71319-5
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7885.7
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
072 7 $a TJFC $2 thema
082 0 4 $a 621.392 $2 23
090 $a TK7885.7 $b .M498 2021
100 1 $a Mehta, Ashok B. $3 674857
245 1 0 $a Introduction to SystemVerilog $h [electronic resource] / $c by Ashok B. Mehta.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2021.
300 $a xxxv, 852 p. : $b ill., digital ; $c 24 cm.
505 0 $a Introduction -- Data Types -- Arrays -- Queues -- Structures -- Packages -- Class -- SystemVerilog 'module' -- SystemVerilog 'program' -- Interfaces -- Operators -- Constrained Random Test Generation and Verification -- SystemVerilog Assertions -- Functional Coverage -- SystemVerilog Processes -- Procedural programming statements -- Processes -- Tasks and Functions -- Clocking Blocks -- Checkers -- Inter-process communication and synchronization -- Utility System tasks and functions.
520 $a This book provides a hands-on, application-oriented guide to the entire IEEE standard 1800 SystemVerilog language. Readers will benefit from the step-by-step approach to learning the language and methodology nuances, which will enable them to design and verify complex ASIC/SoC and CPU chips. The author covers the entire spectrum of the language, including random constraints, SystemVerilog Assertions, Functional Coverage, Class, checkers, interfaces, and Data Types, among other features of the language. Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the complex task of multi-million gate ASIC designs. Provides comprehensive coverage of the entire IEEE standard SystemVerilog language; Covers important topics such as constrained random verification, SystemVerilog Class, Assertions, Functional coverage, data types, checkers, interfaces, processes and procedures, among other language features; Uses easy to understand examples and simulation logs; examples are simulatable and will be provided online; Written by an experienced, professional end-user of ASIC/SoC/CPU and FPGA designs. This is quite a comprehensive work. It must have taken a long time to write it. I really like that the author has taken apart each of the SystemVerilog constructs and talks about them in great detail, including example code and simulation logs. For example, there is a chapter dedicated to arrays, and another dedicated to queues - that is great to have! The Language Reference Manual (LRM) is quite dense and difficult to use as a text for learning the language. This book explains semantics at a level of detail that is not possible in an LRM. This is the strength of the book. This will be an excellent book for novice users and as a handy reference for experienced programmers. Mark Glasser Cerebras Systems.
650 0 $a SystemVerilog (Computer hardware description language) $3 670683
650 1 4 $a Circuits and Systems. $3 274416
650 2 4 $a Processor Architectures. $3 274498
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer Nature eBook
856 4 0 $u https://doi.org/10.1007/978-3-030-71319-5
950 $a Engineering (SpringerNature-11647)