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Design and test strategies for 2D/3D...

Manna, Kanchan.

Design and test strategies for 2D/3D integration for NoC-based multicore architectures

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Design and test strategies for 2D/3D integration for NoC-based multicore architecturesby Kanchan Manna, Jimson Mathew.
作者:	Manna, Kanchan.
其他作者:	Mathew, Jimson.
出版者:	Cham :Springer international Publishing :2020.
面頁冊數:	xii, 162 p. :ill., digital ;24 cm.
Contained By:	Springer eBooks
標題:	Networks on a chipDesign.
電子資源:	https://doi.org/10.1007/978-3-030-31310-4
ISBN:	9783030313104$q(electronic bk.)

Design and test strategies for 2D/3D integration for NoC-based multicore architectures
Manna, Kanchan.

Design and test strategies for 2D/3D integration for NoC-based multicore architectures[electronic resource] /by Kanchan Manna, Jimson Mathew. - Cham :Springer international Publishing :2020. - xii, 162 p. :ill., digital ;24 cm.

introduction to Network-on-Chip Designs and Tests -- iterative Mapping with Through Silicon Via (TSV) placement for 3D-NoC-based multicore systems -- A constructive Heuristic for integrated mapping and TSV Placement for 3D-NoC-based multicore systems -- Discrete Particle Swarm Optimization for integrated mapping and TSV Placement for 3D-NoC-based multicore systems -- Temperature-aware application mapping strategy for 2D-NoC-based multicore systems -- Temperature-aware design strategy for 3D-NoC-based multicore systems -- Temperature-aware test strategy for 2D as well as 3D-NoC-based multicore systems.

This book covers various aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems. it gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling for NoC-based multicores. The authors describe the use of the integer Line Programming (iLP) technique for smaller benchmarks and a Particle Swarm Optimization (PSO) to get a near optimal mapping and test schedule for bigger benchmarks. The PSO-based approach is also augmented with several innovative techniques to get the best possible solution. The tradeoff between performance (communication or test time) of the system and thermal-safety is also discussed, based on designer specifications. Provides a single-source reference to design and test for circuit and system-level approaches to (NoC) based multicore systems; Gives a complete account of the state-of-the-art and emerging techniques for near optimal mapping and test scheduling in (NoC) based multicore systems; Organizes chapters systematically and hierarchically, rather than in an ad hoc manner, covering aspects of optimization in design and testing of Network-on-Chip (NoC) based multicore systems.

ISBN: 9783030313104$q(electronic bk.)

Standard No.: 10.1007/978-3-030-31310-4doiSubjects--Topical Terms:

674842
Networks on a chip
--Design.

LC Class. No.: TK5105.546 / .M366 2020

Dewey Class. No.: 621.381531

Design and test strategies for 2D/3D integration for NoC-based multicore architectures
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