國立高雄大學圖資館 |

語系: 繁體中文

說明(常見問題)

圖資館首頁

登入

回首頁 到查詢結果 [ subject:"Logic Design." ]

切換: 標籤 | MARC模式 | ISBD

Testing of interposer-based 2.5D int...

Chakrabarty, Krishnendu.

Testing of interposer-based 2.5D integrated circuits

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Testing of interposer-based 2.5D integrated circuitsby Ran Wang, Krishnendu Chakrabarty.
作者:	Wang, Ran.
其他作者:	Chakrabarty, Krishnendu.
出版者:	Cham :Springer International Publishing :2017.
面頁冊數:	xiv, 182 p. :ill. (some col.), digital ;24 cm.
Contained By:	Springer eBooks
標題:	Integrated circuits.
電子資源:	http://dx.doi.org/10.1007/978-3-319-54714-5
ISBN:	9783319547145$q(electronic bk.)

Testing of interposer-based 2.5D integrated circuits
Wang, Ran.

Testing of interposer-based 2.5D integrated circuits[electronic resource] /by Ran Wang, Krishnendu Chakrabarty. - Cham :Springer International Publishing :2017. - xiv, 182 p. :ill. (some col.), digital ;24 cm.

Introduction -- Pre-Bond Testing of the Silicon Interposer -- Post-Bond Scan-based Testing of Interposer Interconnects -- Test Architecture and Test-Path Scheduling -- Built-In Self-Test -- ExTest Scheduling and Optimization -- A Programmable Method for Low-Power Scan Shift in SoC Dies -- Conclusions.

This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay faults; Provides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standard; Discusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC die; Includes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs.

ISBN: 9783319547145$q(electronic bk.)

Standard No.: 10.1007/978-3-319-54714-5doiSubjects--Topical Terms:

190434
Integrated circuits.

LC Class. No.: TK7874

Dewey Class. No.: 621.3815

Testing of interposer-based 2.5D integrated circuits
LDR:02655nmm a2200313 a 4500 001 509170
003 DE-He213
005 20170914165946.0
006 m d
007 cr nn 008maaau
008 171121s2017 gw s 0 eng d
020 $a 9783319547145$q(electronic bk.)
020 $a 9783319547138$q(paper)
024 7 $a 10.1007/978-3-319-54714-5 $2 doi
035 $a 978-3-319-54714-5
040 $a GP $c GP
041 0 $a eng
050 4 $a TK7874
072 7 $a TJFC $2 bicssc
072 7 $a TEC008010 $2 bisacsh
082 0 4 $a 621.3815 $2 23
090 $a TK7874 $b .W246 2017
100 1 $a Wang, Ran. $3 775797
245 1 0 $a Testing of interposer-based 2.5D integrated circuits $h [electronic resource] / $c by Ran Wang, Krishnendu Chakrabarty.
260 $a Cham : $b Springer International Publishing : $b Imprint: Springer, $c 2017.
300 $a xiv, 182 p. : $b ill. (some col.), digital ; $c 24 cm.
505 0 $a Introduction -- Pre-Bond Testing of the Silicon Interposer -- Post-Bond Scan-based Testing of Interposer Interconnects -- Test Architecture and Test-Path Scheduling -- Built-In Self-Test -- ExTest Scheduling and Optimization -- A Programmable Method for Low-Power Scan Shift in SoC Dies -- Conclusions.
520 $a This book provides readers with an insightful guide to the design, testing and optimization of 2.5D integrated circuits. The authors describe a set of design-for-test methods to address various challenges posed by the new generation of 2.5D ICs, including pre-bond testing of the silicon interposer, at-speed interconnect testing, built-in self-test architecture, extest scheduling, and a programmable method for low-power scan shift in SoC dies. This book covers many testing techniques that have already been used in mainstream semiconductor companies. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 2.5D ICs a reality and commercially viable. Provides a single-source guide to the practical challenges in testing of 2.5D ICs; Presents an efficient method to locate defects in a passive interposer before stacking; Describes an efficient interconnect-test solution to target through-silicon vias (TSVs), the redistribution layer, and micro-bumps for shorts, opens, and delay faults; Provides a built-in self-test (BIST) architecture that can be enabled by the standard TAP controller in the IEEE 1149.1 standard; Discusses two ExTest scheduling strategies to implement interconnect testing between tiles inside an SoC die; Includes a programmable method for shift-clock stagger assignment to reduce power supply noise during SoC die testing in 2.5D ICs.
650 0 $a Integrated circuits. $3 190434
650 1 4 $a Engineering. $3 210888
650 2 4 $a Circuits and Systems. $3 274416
650 2 4 $a Processor Architectures. $3 274498
650 2 4 $a Logic Design. $3 276275
700 1 $a Chakrabarty, Krishnendu. $3 255103
710 2 $a SpringerLink (Online service) $3 273601
773 0 $t Springer eBooks
856 4 0 $u http://dx.doi.org/10.1007/978-3-319-54714-5
950 $a Engineering (Springer-11647)