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System level design model with reuse...

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Cavalloro, Patrizia.

System level design model with reuse of system IP

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	System level design model with reuse of system IPedited by Patrizia Cavalloro ... [et al.].
其他作者:	Cavalloro, Patrizia.
出版者:	Boston :Springer Science + Business Media, Inc.,c2004.
面頁冊數:	211 p. :ill., digital ;25 cm.
Contained By:	Springer e-books
標題:	Systems on a chipDesign and construction.
電子資源:	http://libsw.nuk.edu.tw:81/login?url=http://dx.doi.org/10.1007/b105966
ISBN:	9780306487330 (electronic bk.)

System level design model with reuse of system IP
System level design model with reuse of system IP[electronic resource] /edited by Patrizia Cavalloro ... [et al.]. - Boston :Springer Science + Business Media, Inc.,c2004. - 211 p. :ill., digital ;25 cm.

ISBN: 9780306487330 (electronic bk.)Subjects--Topical Terms:

242476
Systems on a chip
--Design and construction.

LC Class. No.: TK7895.E42 / S97 2004

Dewey Class. No.: 004.6

System level design model with reuse of system IP
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