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A redundant digit floating point system.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	A redundant digit floating point system.
作者:	Fahmy, Hossam Aly Hassan.
面頁冊數:	146 p.
附註:	Adviser: Michael J. Flynn.
附註:	Source: Dissertation Abstracts International, Volume: 64-05, Section: B, page: 2314.
Contained By:	Dissertation Abstracts International64-05B.
標題:	Engineering, Electronics and Electrical.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3090583
ISBN:	0496383051

A redundant digit floating point system.
Fahmy, Hossam Aly Hassan.

A redundant digit floating point system. [electronic resource] - 146 p.

Adviser: Michael J. Flynn.

Thesis (Ph.D.)--Stanford University, 2003.

A partially redundant number system is used as an internal format for floating point arithmetic operations. The redundant number system is based on signed digits and enables carry free arithmetic operations to improve the performance. Conversion from the proposed internal format back to the standard IEEE format is done only when an operand is written to memory. A detailed discussion of an adder and a multiplier using the proposed format is presented and the specific challenges of the designs are explained. Beside the redundancy, the proposed units include further enhancements that increase the floating point performance such as a hexadecimal based number format and a postponed rounding technique.

ISBN: 0496383051Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

A redundant digit floating point system.
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245 1 2 $a A redundant digit floating point system. $h [electronic resource]
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500 $a Source: Dissertation Abstracts International, Volume: 64-05, Section: B, page: 2314.
502 $a Thesis (Ph.D.)--Stanford University, 2003.
520 # $a A partially redundant number system is used as an internal format for floating point arithmetic operations. The redundant number system is based on signed digits and enables carry free arithmetic operations to improve the performance. Conversion from the proposed internal format back to the standard IEEE format is done only when an operand is written to memory. A detailed discussion of an adder and a multiplier using the proposed format is presented and the specific challenges of the designs are explained. Beside the redundancy, the proposed units include further enhancements that increase the floating point performance such as a hexadecimal based number format and a postponed rounding technique.
520 # $a A time delay model is developed and applied to analytically predict the performance of the floating point units. The predicted delays are then compared to state-of-the-art designs. The comparison is done over a range of operand widths, fan-in and radices to show the merits of each implementation. The proposed system achieves better performance for double precision and larger operand width. Transistor simulation of the complete adder and multiplier confirm the performance advantage predicted by the analytical model. A brief description of a divider using; the proposed format is also presented.
520 # $a Arithmetic operations are among the most basic instructions in microprocessors, digital signal processors and graphics accelerators. Addition is the most frequent arithmetic operation in numerically intensive applications. Multiplication follows closely and then division and other elementary functions. The speed of those arithmetic operations is also often directly linked to the overall performance of the computers. The work presented in this thesis proposes several techniques to improve the effectiveness of floating point arithmetic units.
520 # $a The proposed internal format and arithmetic units comply with all the rounding modes of the IEEE 754 floating point standard.
590 $a School code: 0212.
650 # 0 $a Engineering, Electronics and Electrical. $3 226981
650 # 0 $a Computer Science. $3 212513
710 0 # $a Stanford University. $3 212607
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790 1 0 $a Flynn, Michael J., $e advisor
791 $a Ph.D.
792 $a 2003
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