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Interconnect performance in 3-dimensional integrated circuits.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Interconnect performance in 3-dimensional integrated circuits.
作者:	Souri, Shukri Jeries.
面頁冊數:	140 p.
附註:	Adviser: Krishna C. Saraswat.
附註:	Source: Dissertation Abstracts International, Volume: 64-09, Section: B, page: 4539.
Contained By:	Dissertation Abstracts International64-09B.
標題:	Engineering, Electronics and Electrical.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3104152
ISBN:	0496517201

Interconnect performance in 3-dimensional integrated circuits.
Souri, Shukri Jeries.

Interconnect performance in 3-dimensional integrated circuits. [electronic resource] - 140 p.

Adviser: Krishna C. Saraswat.

Thesis (Ph.D.)--Stanford University, 2003.

Furthermore, an analytical thermal model incorporating the effect of vias as efficient heat conduction paths is developed to analyze the thermal behavior of 3-D systems. It is shown that active layer temperatures in 3-D circuits are dependent on the configuration of devices and operating frequency. The lowest die temperature predicted for 3-D is 99°C, for constant speed, and the highest at 149°C, for twice the speed, with 2-D operating at 104°C. 3-D integration also shows a reduction in the energy dissipated during a switching event by 15% due to the decreased wiring requirement and interconnect capacitance.

ISBN: 0496517201Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Interconnect performance in 3-dimensional integrated circuits.
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520 # $a Furthermore, an analytical thermal model incorporating the effect of vias as efficient heat conduction paths is developed to analyze the thermal behavior of 3-D systems. It is shown that active layer temperatures in 3-D circuits are dependent on the configuration of devices and operating frequency. The lowest die temperature predicted for 3-D is 99°C, for constant speed, and the highest at 149°C, for twice the speed, with 2-D operating at 104°C. 3-D integration also shows a reduction in the energy dissipated during a switching event by 15% due to the decreased wiring requirement and interconnect capacitance.
520 # $a The reduction in the wire length distribution and in chip area is estimated by applying Rent's Rule to a 3-D logic arrangement and determining the fraction of interconnects replaced with VILICs. Results of this comprehensive analytical treatment show that the area can be reduced by a third at the 50nm technology node as projected by the International Technology Roadmap for Semiconductors. The operating frequency of these 3-D circuits can also exhibit a two-fold increase over 2-D through the rerouting and resizing of wires in the interconnect network.
520 # $a The speed of deep submicron very large scale integrated circuits is being increasingly dominated by interconnects due to decreasing wire pitch, increasing circuit complexity and die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (2-D) integrated circuits may not be suitable. The introduction of Copper, low dielectric constant materials and hierarchical interconnect networks have limited ability in alleviating the wiring problem. A novel 3-dimensional (3-D) chip design methodology is proposed to relieve the interconnect bottleneck. Here, active devices, such as transistors or optical transceivers, are arranged in a stacked 3-D array of active layers, each separated vertically by wiring layers. By exploiting the vertical dimension for interconnectivity, critical wires of performance limiting lengths in a 2-D arrangement can be replaced with short, vertical inter-layer interconnections (VILICs) in 3-D. This methodology reduces the wire length distribution, chip area and improves circuit performance. 3-D designs also facilitate the integration of heterogeneous technologies to realize a System-on-Chip (SoC) design.
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