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Achieving scalable hardware verification with symbolic simulation.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Achieving scalable hardware verification with symbolic simulation.
作者:	Bertacco, Valeria Maria.
面頁冊數:	165 p.
附註:	Adviser: Kunle Olukotun.
附註:	Source: Dissertation Abstracts International, Volume: 64-09, Section: B, page: 4515.
Contained By:	Dissertation Abstracts International64-09B.
標題:	Engineering, Electronics and Electrical.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3104197
ISBN:	0496517651

Achieving scalable hardware verification with symbolic simulation.
Bertacco, Valeria Maria.

Achieving scalable hardware verification with symbolic simulation. [electronic resource] - 165 p.

Adviser: Kunle Olukotun.

Thesis (Ph.D.)--Stanford University, 2003.

Both of these techniques have been tested on the ISCAS and Logic Synthesis benchmark suites. The results show that the first technique can simulate very large trace sets in parallel, maintaining a simulation speed and memory profile that are much closer to logic simulation. The second technique is effective in reducing the memory requirements of symbolic simulation while preserving an exact state exploration.

ISBN: 0496517651Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Achieving scalable hardware verification with symbolic simulation.
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520 # $a Both of these techniques have been tested on the ISCAS and Logic Synthesis benchmark suites. The results show that the first technique can simulate very large trace sets in parallel, maintaining a simulation speed and memory profile that are much closer to logic simulation. The second technique is effective in reducing the memory requirements of symbolic simulation while preserving an exact state exploration.
520 # $a In recent years, the complexity of digital integrated circuit (IC) designs has grown at a challenging pace. Within this context, proper verification of an IC design has become a central aspect of the development cycle. Logic simulation is the accepted method for verification because of its scalability, although it can only visits a small fraction of the state space. Symbolic simulation is an alternative method that is attracting increasing interest because it can explore a major portion of the circuit's state space without the need of design-specific tests. The limiting factor to the mainstream deployment of this approach has been its complexity and unpredictable run-time behavior.
520 # $a This thesis presents two new symbolic simulation based approaches to the verification problem that radically improve scalability and narrow the performance gap between design complexity and verification. The first technique, Cycle-Based Symbolic Simulation, is a unique combination of formal methods and logic simulation to stimulate a circuit with a very large number of input combinations in parallel through the use of a parametric form. This approach maintains a high degree of scalability while achieving better efficiency than logic simulation.
520 # $a To better exploit the use of parameterization, Disjoint Support Decomposition Based Symbolic Simulation, our second technique, exploits the disjoint support decomposition (DSD) properties of the state functions. We develop a new algorithm that exposes the DSD of a Boolean function by restructuring its BDD representation. The new algorithm is very efficient in the sense that it has worst-case complexity that is only quadratic in the size of the initial BDD. We deployed this algorithm to find the DSD of the state functions in symbolic simulation, which we then use to generate a more compact, but exact, parametric form.
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