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On-chip wires :Scaling and efficiency.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	On-chip wires :
其他題名:	Scaling and efficiency.
作者:	Ho, Ronald.
面頁冊數:	143 p.
附註:	Adviser: Mark Horowitz.
附註:	Source: Dissertation Abstracts International, Volume: 64-09, Section: B, page: 4521.
Contained By:	Dissertation Abstracts International64-09B.
標題:	Engineering, Electronics and Electrical.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3104240
ISBN:	0496518089

On-chip wires :Scaling and efficiency.
Ho, Ronald.

On-chip wires :Scaling and efficiency. [electronic resource] - 143 p.

Adviser: Mark Horowitz.

Thesis (Ph.D.)--Stanford University, 2003.

Recent years have seen an increase in the importance of on-chip wires, as they have slowed down and gates have sped up. This dissertation takes a close look at the story of wire scaling. It forecasts wire and gate characteristics from the Semiconductor Industry Association roadmap and combines them into performance metrics, showing how the ratio of wire delays to gate delays scales slowly for scaled-length wires and grows rapidly for fixed-length wires.

ISBN: 0496518089Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

On-chip wires :Scaling and efficiency.
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520 # $a Recent years have seen an increase in the importance of on-chip wires, as they have slowed down and gates have sped up. This dissertation takes a close look at the story of wire scaling. It forecasts wire and gate characteristics from the Semiconductor Industry Association roadmap and combines them into performance metrics, showing how the ratio of wire delays to gate delays scales slowly for scaled-length wires and grows rapidly for fixed-length wires.
520 # $a This duality of "fast local wires" contrasted with "slow global wires" affects how we approach VLSI designs. First, CAD place-and-route tools must improve to keep up with growing die complexity and more local blocks gathered on a chip. Second, modular architectures can effectively exploit the dual nature of wires, using wide global buses of high bandwidth to offset long wire latencies.
520 # $a Using such wide and long global buses can burn a great deal of power, especially if built with traditional delay-optimal CMOS repeaters. Traditional repeaters can be sized and spaced to save about 30% in energy for only a 10% delay penalty. Because this 30% of energy savings is not a lot, techniques for running global wires at a reduced voltage can be very important. These include NMOS drivers, overdrive pre-emphasis, and voltage pre-equalization. Using these circuit techniques offers an order-of-magnitude in energy savings for no effective slowdown. Experimental results on a 180nm testchip validate this 10x savings in energy over 10mm long on-chip buses, running at 1 token per 10 gate delays. Further experimental data shows receiver input offsets under 90mV, with input offset compensation leading to residual input uncertainties of around 15mV.
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