國立高雄大學圖資館 |

Language: English

Back

Design flow for deep sub-micron integrated-circuits

Record Type:	Electronic resources : Monograph/item
Title/Author:	Design flow for deep sub-micron integrated-circuits
Author:	Mo, Fan.
Description:	362 p.
Notes:	Chair: Robert K. Brayton.
Notes:	Source: Dissertation Abstracts International, Volume: 65-02, Section: B, page: 0930.
Contained By:	Dissertation Abstracts International65-02B.
Subject:	Engineering, Electronics and Electrical.
Online resource:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3121619
ISBN:	0496689703

Design flow for deep sub-micron integrated-circuits
Mo, Fan.

Design flow for deep sub-micron integrated-circuits [electronic resource] - 362 p.

Chair: Robert K. Brayton.

Thesis (Ph.D.)--University of California, Berkeley, 2003.

Regularity is a feature, which can provide better guarantees that the layout designed by a CAD tool is replicated in the fabrication. As the limits of the mask-making system (finite aperture of projection) are reached with smaller geometries, the actual layout patterns on the wafer differ from that produced by a CAD tool. Although pre-distortion can be added to offset some of the real distortions, the number of layout patterns generated by a conventional design flow can make this task take an unreasonable amount of time and generate an enormous data set. Beyond what optimal pre-distortion could do, regular circuit and interconnection structures can reduce variations further. Another motivation for using regularity is the timing closure problem, which arises because the design flow is sequential; early steps need to predict what the later steps will do. Inaccurate prediction leads to wrong decisions, which can only be discovered later, making design iteration necessary. Preventing such iterations is difficult, but use of regular structures, can make estimation much more accurate.

ISBN: 0496689703Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Design flow for deep sub-micron integrated-circuits
LDR:02718nmm _2200277 _450 001 162428
005 20051017073445.5
008 230606s2003 eng d
020 $a 0496689703
035 $a 00148929
035 $a 162428
040 $a UnM $c UnM
100 0 $a Mo, Fan. $3 227565
245 1 0 $a Design flow for deep sub-micron integrated-circuits $h [electronic resource]
300 $a 362 p.
500 $a Chair: Robert K. Brayton.
500 $a Source: Dissertation Abstracts International, Volume: 65-02, Section: B, page: 0930.
502 $a Thesis (Ph.D.)--University of California, Berkeley, 2003.
520 # $a Regularity is a feature, which can provide better guarantees that the layout designed by a CAD tool is replicated in the fabrication. As the limits of the mask-making system (finite aperture of projection) are reached with smaller geometries, the actual layout patterns on the wafer differ from that produced by a CAD tool. Although pre-distortion can be added to offset some of the real distortions, the number of layout patterns generated by a conventional design flow can make this task take an unreasonable amount of time and generate an enormous data set. Beyond what optimal pre-distortion could do, regular circuit and interconnection structures can reduce variations further. Another motivation for using regularity is the timing closure problem, which arises because the design flow is sequential; early steps need to predict what the later steps will do. Inaccurate prediction leads to wrong decisions, which can only be discovered later, making design iteration necessary. Preventing such iterations is difficult, but use of regular structures, can make estimation much more accurate.
520 # $a The following developments have been made to implement a tinting-driven Module-Based chip design flow: (1) new regular circuit structures and their design methodologies, (2) a new integrated placement and routing algorithm that simplifies the standard-cell physical design, (3) a new block-level placement and routing algorithm with buffer insertion and (4) a multi-version approach allowing each module to carry several versions that can be selected by the block-level physical design algorithm. Test results show that our design flow can reach timing closure much faster than the Physical Synthesis flow and achieve shorter clock cycle.
590 $a School code: 0028.
650 # 0 $a Engineering, Electronics and Electrical. $3 226981
690 $a 0544
710 0 # $a University of California, Berkeley. $3 212474
773 0 # $g 65-02B. $t Dissertation Abstracts International
790 $a 0028
790 1 0 $a Brayton, Robert K., $e advisor
791 $a Ph.D.
792 $a 2003
856 4 0 $u http://libsw.nuk.edu.tw/login?url=http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3121619 $z http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3121619