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Digital calibration for low-power high-performance A/D conversion

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Digital calibration for low-power high-performance A/D conversion
作者:	Murmann, Boris.
面頁冊數:	180 p.
附註:	Chair: Bernhard E. Boser.
附註:	Source: Dissertation Abstracts International, Volume: 65-02, Section: B, page: 0931.
Contained By:	Dissertation Abstracts International65-02B.
標題:	Engineering, Electronics and Electrical.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3121625
ISBN:	0496689762

Digital calibration for low-power high-performance A/D conversion
Murmann, Boris.

Digital calibration for low-power high-performance A/D conversion [electronic resource] - 180 p.

Chair: Bernhard E. Boser.

Thesis (Ph.D.)--University of California, Berkeley, 2003.

In the multi-bit first stage of a 12-b, 75-MS/s proof-of-concept prototype, the proposed concept resulted in power savings greater than 60% over a conventional implementation. The experimental converter was fabricated in a 0.35-mum double-poly, quadruple-metal CMOS technology and achieves typical differential and integral nonlinearity within 0.6LSB and 0.7LSB respectively. At Nyquist input frequencies, the measured signal-to-noise ratio is 67dB and the total harmonic distortion is -74dB. The ADC consumes 290mW from a 3V supply and occupies 7.9mm2.

ISBN: 0496689762Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Digital calibration for low-power high-performance A/D conversion
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520 # $a In the multi-bit first stage of a 12-b, 75-MS/s proof-of-concept prototype, the proposed concept resulted in power savings greater than 60% over a conventional implementation. The experimental converter was fabricated in a 0.35-mum double-poly, quadruple-metal CMOS technology and achieves typical differential and integral nonlinearity within 0.6LSB and 0.7LSB respectively. At Nyquist input frequencies, the measured signal-to-noise ratio is 67dB and the total harmonic distortion is -74dB. The ADC consumes 290mW from a 3V supply and occupies 7.9mm2.
520 # $a This dissertation explores the opportunity to reduce ADC power dissipation by leveraging digital signal processing capabilities in fine line integrated circuit technology. The proposed digitally assisted pipelined ADC uses a statistics based system identification technique as an enabling element to replace precision residue amplifiers with simple open-loop gain stages. The digital compensation of analog circuit distortion eliminates one key factor in the classical noise-speed-linearity constraint loop and thereby enables a significant power reduction.
520 # $a With the advent of powerful digital signal processing in portable electronic applications, we have seen a growing, unsatisfied demand for power efficient, high-speed and high-resolution analog-to-digital converters (ADCs). While technology scaling has led to revolutionary gains in digital computing power and energy efficiency, progress in analog-to-digital conversion interfaces has been comparatively slow.
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