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The SFRA :A fixed frequency FPGA architecture

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	The SFRA :
其他題名:	A fixed frequency FPGA architecture
作者:	Weaver, Nicholas Croyle.
面頁冊數:	176 p.
附註:	Chair: John Wawrzynek.
附註:	Source: Dissertation Abstracts International, Volume: 65-02, Section: B, page: 0853.
Contained By:	Dissertation Abstracts International65-02B.
標題:	Computer Science.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3121746
ISBN:	0496690973

The SFRA :A fixed frequency FPGA architecture
Weaver, Nicholas Croyle.

The SFRA :A fixed frequency FPGA architecture [electronic resource] - 176 p.

Chair: John Wawrzynek.

Thesis (Ph.D.)--University of California, Berkeley, 2003.

An alternative approach, a Fixed-Frequency FPGA, has an intrinsic clock rate at which all designs will operate after automatic or manual modification. Fixed-Frequency FPGAs offer significant advantages in computational throughput, throughput per unit area, and ease of integration as a computational coprocessor in a system on a chip. Previous Fixed-Frequency FPGAs either suffered from restrictive interconnects, application restrictions, or issues arising from the need for new toolflows.

ISBN: 0496690973Subjects--Topical Terms:

212513
Computer Science.

The SFRA :A fixed frequency FPGA architecture
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520 # $a An alternative approach, a Fixed-Frequency FPGA, has an intrinsic clock rate at which all designs will operate after automatic or manual modification. Fixed-Frequency FPGAs offer significant advantages in computational throughput, throughput per unit area, and ease of integration as a computational coprocessor in a system on a chip. Previous Fixed-Frequency FPGAs either suffered from restrictive interconnects, application restrictions, or issues arising from the need for new toolflows.
520 # $a C-slow retiming, a process of increasing the throughput by interleaving independent streams of execution, is used to automatically modify designs so they operate at the array's intrinsic clock frequency. An additional C-slowing tool improves designs targeting conventional FPGAs to isolate the benefits of this transformation from those arising from fixed frequency operation. This semantic transformation can even be applied to a microprocessor, automatically creating an interleaved multithreaded architecture.
520 # $a Field Programmable Gate Arrays (FPGAs) are synchronous digital devices used to realize digital designs on a programmable fabric. Conventional FPGAs use design dependent clocking, so the resulting clock frequency is dependent on the user design and the mapping process.
520 # $a Since the Corner Turn topology maintains conventional placement properties, this thesis defines a Fixed-Frequency FPGA architecture which is placement and tool compatible with Xilinx Virtex FPGAs. By defining the architecture, estimating the area and performance cost, and providing routing and retiming tools, this thesis directly compares the costs and benefits of a Fixed-Frequency FPGA with a commercial FPGA.
520 # $a This thesis proposes a new interconnect topology, a "Corner Turn" network, which maintains the placement properties and upstream toolflows of a conventional FPGA while allowing efficient, pipelined, fixed frequency operation. Global routing for this topology uses efficient, polynomial time heuristics and complete searches. Detailed routing uses channel-independent packing.
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