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Nano-scaled logic and memory devices :Modeling and fabrication

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Nano-scaled logic and memory devices :
其他題名:	Modeling and fabrication
作者:	Xuan, Peiqi.
面頁冊數:	126 p.
附註:	Chair: Jeffrey Bokor.
附註:	Source: Dissertation Abstracts International, Volume: 65-02, Section: B, page: 0950.
Contained By:	Dissertation Abstracts International65-02B.
標題:	Engineering, Electronics and Electrical.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3121764
ISBN:	0496691155

Nano-scaled logic and memory devices :Modeling and fabrication
Xuan, Peiqi.

Nano-scaled logic and memory devices :Modeling and fabrication [electronic resource] - 126 p.

Chair: Jeffrey Bokor.

Thesis (Ph.D.)--University of California, Berkeley, 2003.

A correct threshold voltage (Vt) can be achieved only by gate workfunction engineering in sub-30nm transistors. NiSi is proposed as a single gate material for multiple Vt CMOS applications because the workfunction of NiSi can be continuously adjusted over a large range by dopants implanted into the silicon film before silicidation. Furthermore, the NiSi gate has excellent compatibility with the current CMOS process because it causes no degradation of the resulting MOSFET performance. After all, nickel silicide is highly advantageous as a single gate material for future CMOS technologies.

ISBN: 0496691155Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Nano-scaled logic and memory devices :Modeling and fabrication
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520 # $a A correct threshold voltage (Vt) can be achieved only by gate workfunction engineering in sub-30nm transistors. NiSi is proposed as a single gate material for multiple Vt CMOS applications because the workfunction of NiSi can be continuously adjusted over a large range by dopants implanted into the silicon film before silicidation. Furthermore, the NiSi gate has excellent compatibility with the current CMOS process because it causes no degradation of the resulting MOSFET performance. After all, nickel silicide is highly advantageous as a single gate material for future CMOS technologies.
520 # $a Lateral solid-phase-epitaxy (SPE) is a practical approach to realizing the UTB structure with good uniformity and controllability of the thin Si channel film. SPEFETs are fabricated, and the quality of the SPE films is investigated. Within a short SPE range (≤60nm), the resulting film has good quality close to that of a perfect Si film, and good device performance has been achieved. The easy integration of SPEFET with bulk MOSFET makes it suitable for sub-50nm device generations.
520 # $a The fully depleted structure is also applied to flash memory, and the resulting FinFET SONGS can be successfully scaled to sub-40nm. The large V t windows and high current ratio between programmed/erased states enable multi-bit storage for even higher storage density. Good program/erase speeds, endurance and retention are demonstrated in FinFET SONGS memory devices. Devices fabricated on (100) sidewall surfaces show more resistance to electrical stress than do (110) devices. The FinFET SONGS device is a promising candidate for sub-100nm embedded flash memories.
520 # $a This dissertation investigates both the modeling and fabrication of ultra-thin-body (UTB) and double gate (DG) MOSFETs, which are proposed to suppress short channel effects (SCE) in nano-scaled MOSFETs. An analytic model is developed to evaluate the effectiveness of the structures. The minimum channel length with certain performance criteria can be derived from the physical dimensions of the transistor. The 2D effects in both the body and the high kappa gate dielectric are included. The influences of high body doping and pocket implants on SCE are also modeled. The results of the analytical model form the basis of the subsequent discussion of device design and fabrication.
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