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Synergistic caching in single-chip m...

Harris, Sarah Leilani.

Synergistic caching in single-chip multiprocessors.

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Synergistic caching in single-chip multiprocessors.
作者:	Harris, Sarah Leilani.
面頁冊數:	104 p.
附註:	Adviser: William James Dally.
附註:	Source: Dissertation Abstracts International, Volume: 66-01, Section: B, page: 0441.
Contained By:	Dissertation Abstracts International66-01B.
標題:	Engineering, Electronics and Electrical.
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3162376
ISBN:	0496963678

Synergistic caching in single-chip multiprocessors.
Harris, Sarah Leilani.

Synergistic caching in single-chip multiprocessors. - 104 p.

Adviser: William James Dally.

Thesis (Ph.D.)--Stanford University, 2005.

For capacity-limited scenarios, synergistic caching takes advantage of the high on-chip bandwidth and low latency of CMPs, minimizes the area dedicated to caching, and takes advantage of sharing to improve performance. The cost of doing this is added hardware in the critical path. Because of these costs, we show that returns are modest for larger cache sizes, making it beneficial to use synergistic caching only when the system is area-constrained, and the user would rather use the area for processing power than for additional levels in the memory hierarchy.

ISBN: 0496963678Subjects--Topical Terms:

226981
Engineering, Electronics and Electrical.

Synergistic caching in single-chip multiprocessors.
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520 # $a For capacity-limited scenarios, synergistic caching takes advantage of the high on-chip bandwidth and low latency of CMPs, minimizes the area dedicated to caching, and takes advantage of sharing to improve performance. The cost of doing this is added hardware in the critical path. Because of these costs, we show that returns are modest for larger cache sizes, making it beneficial to use synergistic caching only when the system is area-constrained, and the user would rather use the area for processing power than for additional levels in the memory hierarchy.
520 # $a In this thesis, we explore the direction of caching systems as they are driven by developing technology, particularly the confluence of many processors onto a single die. We introduce Synergistic Caching (SC) to explore the advantages uncovered by these chip multiprocessors (CMPs)---most significantly, high on-chip bandwidth and low latency---to improve the performance of the caching system.
520 # $a We examine a set of five benchmarks and evaluate their performance using a cycle-accurate simulator. Across these benchmarks, we show that the SC system supplies 7--72% of the data that would have otherwise been supplied by main memory and subsequently improves performance by up to 28% for the same applications as compared to an independent L1 caching system. As compared to a shared-L2 caching system of comparable area, the SC system exhibits up to a 92% speedup in execution.
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