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Synthesis of arithmetic circuits FPGA, ASIC and embedded systems /
紀錄類型:
書目-電子資源 : Monograph/item
正題名/作者:
Synthesis of arithmetic circuits Jean-Pierre Deschamps, Gery Jean Antoine Bioul, Gustavo D. Sutter.
其他題名:
FPGA, ASIC and embedded systems /
作者:
Deschamps, Jean-Pierre,
其他作者:
Bioul, Gery Jean Antoine.
出版者:
Hoboken, N.J. :John Wiley,2006.
面頁冊數:
p. cm.
標題:
Computer arithmetic and logic units.
電子資源:
http://www3.interscience.wiley.com/cgi-bin/homepage/?isbn=0471741426
電子資源:
http://www.loc.gov/catdir/toc/ecip057/2005003237.html
電子資源:
http://www.loc.gov/catdir/enhancements/fy0621/2005003237-b.html
電子資源:
http://www.loc.gov/catdir/enhancements/fy0621/2005003237-d.html
ISBN:
0471687839 (cloth)
Synthesis of arithmetic circuits FPGA, ASIC and embedded systems /
Deschamps, Jean-Pierre,1945-.
Synthesis of arithmetic circuits
FPGA, ASIC and embedded systems /[electronic resource] :Jean-Pierre Deschamps, Gery Jean Antoine Bioul, Gustavo D. Sutter. - Hoboken, N.J. :John Wiley,2006. - p. cm.
ISBN: 0471687839 (cloth)
LCCN: 2005003237Subjects--Topical Terms:
246271
Computer arithmetic and logic units.
LC Class. No.: TK7895.A65 / D47 2005
Dewey Class. No.: 621.39/5
Synthesis of arithmetic circuits FPGA, ASIC and embedded systems /
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http://libsw.nuk.edu.tw/login?url=http://www3.interscience.wiley.com/cgi-bin/homepage/?isbn=0471741426
http://www.loc.gov/catdir/toc/ecip057/2005003237.html
http://www.loc.gov/catdir/enhancements/fy0621/2005003237-b.html
http://www.loc.gov/catdir/enhancements/fy0621/2005003237-d.html
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