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A parallel algorithm synthesis proce...

Dunn, Ian N.

A parallel algorithm synthesis procedure for high-performance computer architectures /

紀錄類型:	書目-語言資料,印刷品 : Monograph/item
正題名/作者:	A parallel algorithm synthesis procedure for high-performance computer architectures /Ian N. Dunn and Gerard G.L. Meyer.
作者:	Dunn, Ian N.
其他作者:	Meyer, Gerard G. L.
出版者:	New York :Kluwer Academic/Plenum Publishers,c2003.
面頁冊數:	xi, 108 p. :ill. ;24 cm.
標題:	Computer architecture.
ISBN:	0306477432 :

A parallel algorithm synthesis procedure for high-performance computer architectures /
Dunn, Ian N.

A parallel algorithm synthesis procedure for high-performance computer architectures /Ian N. Dunn and Gerard G.L. Meyer. - New York :Kluwer Academic/Plenum Publishers,c2003. - xi, 108 p. :ill. ;24 cm. - Series in computer science. - Series in computer science (Kluwer Academic/Plenum Publishers).

Includes bibliographical references (p. 103-106) and index.

ISBN: 0306477432 :NT$5293

LCCN: 2003044716Subjects--Topical Terms:

183006
Computer architecture.

LC Class. No.: QA76.642 / .D86 2003

Dewey Class. No.: 005.2/75

A parallel algorithm synthesis procedure for high-performance computer architectures /
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