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LC-Ladder寬頻低雜訊放大器分析與製作 = LC-Ladder b...

國立高雄大學電機工程學系碩士班

LC-Ladder寬頻低雜訊放大器分析與製作 = LC-Ladder broadband Low Noise Amplifier Design and analysis

紀錄類型:	書目-語言資料,印刷品 : 單行本
並列題名:	LC-Ladder broadband Low Noise Amplifier Design and analysis
作者:	謝毅覺,
其他團體作者:	國立高雄大學
出版地:	[高雄市]
出版者:	撰者;
出版年:	2009[民98]
面頁冊數:	107面圖、表 : 30公分;
標題:	WiMAX
標題:	WiMAX
電子資源:	http://handle.ncl.edu.tw/11296/ndltd/50376700669344279895
附註:	指導教授：葉文冠
附註:	參考書目：面
摘要註:	本論文針對WiMAX通訊系統規格設計了二顆CMOS低雜訊放大器，第一顆為應用於2-6GHz之寬頻低雜訊放大器，第二顆為2.4GHz及5.2GHz雙頻低雜訊放大器，均使用台灣積體電路製造公司(TSMC)0.18μm CMOS 製程設計完成。以上晶片均透過國家系統晶片設計中心(Chip Implementation Center, CIC)下線製造。亦透過台南CIC高頻量測系統量測完成。本論文所設計的放大器晶片，對於第一顆所設計的放大器是部分工作的，在1.2V工作電壓下，有11.5mA的電流，功率消耗為13.8mW，量測的數據與模擬的數據有所差距的主要原因為VDD線段的損耗使得MOS偏壓點產生偏差以及電路中的訊號線旁置入dummy使得訊號線與接地端產生下地電容，使頻率偏移。；而第二顆放大器因金屬線段之間產生寄生電容使得電路;mismatch，其量測特性與模擬差異甚大，因此應將較為敏感的訊號金屬線段進行電磁模擬工作以及在電路佈局中加入旁路電容以濾除直流金屬線上多餘的交流雜訊便可得到改善。 In this thesis, I had designed two chips to meet WiMAX communication system standards, The first one is applicable on 2-6 GHz wideband low noise amplifier; the second is useful for 2.4GHz and 5.2GHz dual-band low noise amplifier. The low noise amplifiers were fabricated using TSMC 0.18μm CMOS manufacturing process, the measurement was done by RF measurement lab in Chip Implementation Center (CIC)..The first chip is partial working on 1.2V, with 11.5mA current and 13.8mW power consumption, measurement and simulation data cannot fitting well. The major issue is caused by (1) the loss of metal line influence the bias voltage of MOS, and (2) the ground dummy which placed near the signal path will cause a parasitic capacitor to ground which will cause frequency shifting. Because of the parasitic capacitor which caused circuit mismatch between metal line of signal path, the second cannot meet the simulated data, Thus, it should simulate EM(electric magnetic) with metal line of signal path which is sensitive and used bypass capacitor to filter the noise on the dc metal line that could be improved.

LC-Ladder寬頻低雜訊放大器分析與製作 = LC-Ladder broadband Low Noise Amplifier Design and analysis
謝, 毅覺

LC-Ladder寬頻低雜訊放大器分析與製作 = LC-Ladder broadband Low Noise Amplifier Design and analysis / 謝毅覺撰 - [高雄市] : 撰者, 2009[民98]. - 107面 ; 圖、表 ; 30公分.
指導教授：葉文冠參考書目：面.
WiMAXWiMAX

LC-Ladder寬頻低雜訊放大器分析與製作 = LC-Ladder broadband Low Noise Amplifier Design and analysis
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330 $a 本論文針對WiMAX通訊系統規格設計了二顆CMOS低雜訊放大器，第一顆為應用於2-6GHz之寬頻低雜訊放大器，第二顆為2.4GHz及5.2GHz雙頻低雜訊放大器，均使用台灣積體電路製造公司(TSMC)0.18μm CMOS 製程設計完成。以上晶片均透過國家系統晶片設計中心(Chip Implementation Center, CIC)下線製造。亦透過台南CIC高頻量測系統量測完成。本論文所設計的放大器晶片，對於第一顆所設計的放大器是部分工作的，在1.2V工作電壓下，有11.5mA的電流，功率消耗為13.8mW，量測的數據與模擬的數據有所差距的主要原因為VDD線段的損耗使得MOS偏壓點產生偏差以及電路中的訊號線旁置入dummy使得訊號線與接地端產生下地電容，使頻率偏移。；而第二顆放大器因金屬線段之間產生寄生電容使得電路;mismatch，其量測特性與模擬差異甚大，因此應將較為敏感的訊號金屬線段進行電磁模擬工作以及在電路佈局中加入旁路電容以濾除直流金屬線上多餘的交流雜訊便可得到改善。 In this thesis, I had designed two chips to meet WiMAX communication system standards, The first one is applicable on 2-6 GHz wideband low noise amplifier; the second is useful for 2.4GHz and 5.2GHz dual-band low noise amplifier. The low noise amplifiers were fabricated using TSMC 0.18μm CMOS manufacturing process, the measurement was done by RF measurement lab in Chip Implementation Center (CIC)..The first chip is partial working on 1.2V, with 11.5mA current and 13.8mW power consumption, measurement and simulation data cannot fitting well. The major issue is caused by (1) the loss of metal line influence the bias voltage of MOS, and (2) the ground dummy which placed near the signal path will cause a parasitic capacitor to ground which will cause frequency shifting. Because of the parasitic capacitor which caused circuit mismatch between metal line of signal path, the second cannot meet the simulated data, Thus, it should simulate EM(electric magnetic) with metal line of signal path which is sensitive and used bypass capacitor to filter the noise on the dc metal line that could be improved.
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