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Three-dimensional integrated circuit...

Friedman, Eby G.

Three-dimensional integrated circuit design

紀錄類型:	書目-電子資源 : Monograph/item
正題名/作者:	Three-dimensional integrated circuit designVasilis F. Pavlidis, Eby G. Friedman.
作者:	Pavlidis, Vasilis F.,
其他作者:	Friedman, Eby G.
出版者:	Amsterdam ;Morgan Kaufmann,c2009.
面頁冊數:	xv, 309 p. :ill. ;25 cm.
叢書名:	The Morgan Kaufmann series in systems on silicon
標題:	Integrated circuitsDesign and construction.
電子資源:	An electronic book accessible through the World Wide Web; click for information
電子資源:	http://www.engineeringvillage.com/controller/servlet/OpenURL?genre=book&isbn=9780123743435
ISBN:	9780123743435

Three-dimensional integrated circuit design
Pavlidis, Vasilis F.,1976-

Three-dimensional integrated circuit design[electronic resource] /Vasilis F. Pavlidis, Eby G. Friedman. - Amsterdam ;Morgan Kaufmann,c2009. - xv, 309 p. :ill. ;25 cm. - The Morgan Kaufmann series in systems on silicon.

Includes bibliographical references (p. 289-303) and index.

Chapter 1. Introduction -- Chapter 2. Manufacturing of 3-D Packaged Systems -- Chapter 3. 3-D Integrated Circuit Fabrication Technologies -- Chapter 4. Interconnect Prediction Models -- Chapter 5. Physical Design Techniques for 3-D ICs -- Chapter 6. Thermal Management Techniques -- Chapter 7. Timing Optimization for Two-Terminal Interconnects -- Chapter 8. Timing Optimization for Multi-Terminal Interconnects -- Appendix A: Enumeration of Gate Pairs in a 3-D IC --Appendix B: Formal Proof of Optimum Single Via Placement -- Appendix C: Proof of the Two-Terminal Via Placement Heuristic -- Appendix D: Proof of Condition for Via Placement of Multi-Terminal Nets -- References.

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance.

Electronic reproduction.
Amsterdam :
Elsevier Science & Technology,
2009.

Mode of access: World Wide Web.

ISBN: 9780123743435

Source: 152801:152956Elsevier Science & Technologyhttp://www.sciencedirect.comSubjects--Topical Terms:

184690
Integrated circuits
--Design and construction.Index Terms--Genre/Form:

214472
Electronic books.

LC Class. No.: TK7874 / .P39 2009

Dewey Class. No.: 621.3815

Three-dimensional integrated circuit design
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505 0 $a Chapter 1. Introduction -- Chapter 2. Manufacturing of 3-D Packaged Systems -- Chapter 3. 3-D Integrated Circuit Fabrication Technologies -- Chapter 4. Interconnect Prediction Models -- Chapter 5. Physical Design Techniques for 3-D ICs -- Chapter 6. Thermal Management Techniques -- Chapter 7. Timing Optimization for Two-Terminal Interconnects -- Chapter 8. Timing Optimization for Multi-Terminal Interconnects -- Appendix A: Enumeration of Gate Pairs in a 3-D IC --Appendix B: Formal Proof of Optimum Single Via Placement -- Appendix C: Proof of the Two-Terminal Via Placement Heuristic -- Appendix D: Proof of Condition for Via Placement of Multi-Terminal Nets -- References.
520 $a With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance.
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