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四閘極電晶體具氧化層基體絕緣結構之短通道行為研究 = The Inves...

國立高雄大學電機工程學系碩士班

四閘極電晶體具氧化層基體絕緣結構之短通道行為研究 = The Investigation on Short-Channel Bebavior Model for the SOI Four-Gate Transistor

紀錄類型:	書目-語言資料,印刷品 : 單行本
並列題名:	The Investigation on Short-Channel Bebavior Model for the SOI Four-Gate Transistor
作者:	楊鳴傑,
其他團體作者:	國立高雄大學
出版地:	[高雄市]
出版者:	撰者;
出版年:	民99[2010]
面頁冊數:	76面圖，表 : 30公分;
標題:	多閘極電晶體
標題:	Multiple-Gate Transistors
電子資源:	http://handle.ncl.edu.tw/11296/ndltd/74799974987275825055
摘要註:	為了增強電流的驅動能力和改善短通道特性，金氧半場效電晶體元件之發展已從單閘極傳統平面基材結構(planar SOI single-gate MOSFET)進一步發展具多閘極氧化層基體絕緣結構(SOI multiple-gate MOSFET)；諸如雙閘極(Double-gate)和三閘極(Triple-gate)電晶體具氧化層基體絕緣結構。近年來具氧化層基體絕緣結構之四閘極電晶體已引起廣泛的注意與研究，相較於一般的平面電晶體元件，其通道係藉由電晶體的四個閘極獨立操作加以控制，因此大大的提升數位電路功能應用之靈活性，除此之外，具氧化層基體絕緣結構之四閘極電晶體尚具有以下電路操作之優點:高直流增益(high DC gain)、低功率消耗(low power consumption)、低雜訊操作(low noise operation)與抑制散射效應(immunity of scattering effects)，因此四閘極電晶體已成為電路設計的另一不錯之選擇。本論文乃基於帕森方程式之全二維解與全三維解，成功地推導出四閘極電晶體具氧化層基體絕緣結構之短通道行為解析模型，此模型不僅準確顯示出電位分佈(potential distribution)、短通道臨界電壓縮減(threshold voltage degradation)、汲極偏壓導致能障降低(drain-induced-barrier-lowering)等效應，而且此模型之演算結果與模擬數據相當接近，足以提供基本元件設計之導向，並進而被應用於積體電路之模擬。 In recent years, silicon-on-insulator (SOI) four-gate transistors have already caused extensive attention. With improved current drive and short-channel characteristics, semiconductors depicts not only switch from bulk to SOI, but also evolve from single-gate planar SOI transistors to multiple-gate devices. Among those novel SOI devices, double- and triple-gate transistors have been demonstrated and modeled. However; the SOI four-gate transistor with low-power and low-noise operation, high intrinsic DC gain, radiation hardness that becomes a promising candidate has not been analytically modeled yet.In this thesis, based on the exact solution of the Poisson equation, we successfully develop an analytical short-channel behavior model for SOI four-gate transistor. Without any fitting parameters, these analytical results are useful in predictive compact modeling of SOI four-gate transistor. The model explicitly shows the distribution of electric potential, short channel threshold voltage roll-off, and drain-induced-barrier-lowing (DIBL) effect. The model is verified by published numerical simulations with close agreement. This model not only gives physical insights into the device physics but also offers the basic designing guidance of the SOI four-gate transistor. Due to its computational efficiency, this model can be applied for SPICE simulation.

四閘極電晶體具氧化層基體絕緣結構之短通道行為研究 = The Investigation on Short-Channel Bebavior Model for the SOI Four-Gate Transistor
楊, 鳴傑

四閘極電晶體具氧化層基體絕緣結構之短通道行為研究 = The Investigation on Short-Channel Bebavior Model for the SOI Four-Gate Transistor / 楊鳴傑撰 - [高雄市] : 撰者, 民99[2010]. - 76面 ; 圖，表 ; 30公分.
參考書目：面.
多閘極電晶體Multiple-Gate Transistors

四閘極電晶體具氧化層基體絕緣結構之短通道行為研究 = The Investigation on Short-Channel Bebavior Model for the SOI Four-Gate Transistor
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328 $a 碩士論文--國立高雄大學電機工程學系碩士班
330 $a 為了增強電流的驅動能力和改善短通道特性，金氧半場效電晶體元件之發展已從單閘極傳統平面基材結構(planar SOI single-gate MOSFET)進一步發展具多閘極氧化層基體絕緣結構(SOI multiple-gate MOSFET)；諸如雙閘極(Double-gate)和三閘極(Triple-gate)電晶體具氧化層基體絕緣結構。近年來具氧化層基體絕緣結構之四閘極電晶體已引起廣泛的注意與研究，相較於一般的平面電晶體元件，其通道係藉由電晶體的四個閘極獨立操作加以控制，因此大大的提升數位電路功能應用之靈活性，除此之外，具氧化層基體絕緣結構之四閘極電晶體尚具有以下電路操作之優點:高直流增益(high DC gain)、低功率消耗(low power consumption)、低雜訊操作(low noise operation)與抑制散射效應(immunity of scattering effects)，因此四閘極電晶體已成為電路設計的另一不錯之選擇。本論文乃基於帕森方程式之全二維解與全三維解，成功地推導出四閘極電晶體具氧化層基體絕緣結構之短通道行為解析模型，此模型不僅準確顯示出電位分佈(potential distribution)、短通道臨界電壓縮減(threshold voltage degradation)、汲極偏壓導致能障降低(drain-induced-barrier-lowering)等效應，而且此模型之演算結果與模擬數據相當接近，足以提供基本元件設計之導向，並進而被應用於積體電路之模擬。 In recent years, silicon-on-insulator (SOI) four-gate transistors have already caused extensive attention. With improved current drive and short-channel characteristics, semiconductors depicts not only switch from bulk to SOI, but also evolve from single-gate planar SOI transistors to multiple-gate devices. Among those novel SOI devices, double- and triple-gate transistors have been demonstrated and modeled. However; the SOI four-gate transistor with low-power and low-noise operation, high intrinsic DC gain, radiation hardness that becomes a promising candidate has not been analytically modeled yet.In this thesis, based on the exact solution of the Poisson equation, we successfully develop an analytical short-channel behavior model for SOI four-gate transistor. Without any fitting parameters, these analytical results are useful in predictive compact modeling of SOI four-gate transistor. The model explicitly shows the distribution of electric potential, short channel threshold voltage roll-off, and drain-induced-barrier-lowing (DIBL) effect. The model is verified by published numerical simulations with close agreement. This model not only gives physical insights into the device physics but also offers the basic designing guidance of the SOI four-gate transistor. Due to its computational efficiency, this model can be applied for SPICE simulation.
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